Via-Capping Layer Structure for Low-Resistance Semiconductor Interconnects

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The increasing resistance between wiring and vias in semiconductor devices due to down-scaling poses a challenge, affecting the reliability of semiconductor chips.

Innovation Solution

The semiconductor device design incorporates a lower wiring capping layer and via made of the same material, such as molybdenum, to improve electrical reliability by reducing resistance and enhancing connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If down-scaling of semiconductor devices is implemented to achieve higher integration, then device integration is improved, but resistance between wiring and vias increases

Engineering Contradiction:
Improvedevice integrationVSAvoidelectrical reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies homogeneity by forming the via and lower wiring capping layer from the same material (e.g., molybdenum) through a single etch process. This eliminates material interfaces between the via and capping layer, ensuring uniform electrical properties and reducing resistance at the junction point, thereby maintaining electrical reliability during down-scaling.

Inventive Principle:
Principle #33Homogeneity

Solution Approach 2:

The patent changes the material parameter by selecting a specific material (molybdenum) that serves dual purposes for both the via and capping layer. This parameter change enables the via to protrude through the capping layer without creating additional interfaces, reducing resistance while accommodating the higher integration requirements of down-scaled devices.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If via protrudes through lower wiring capping layer to reduce resistance, then electrical reliability is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical reliabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the via formation process with the lower wiring capping layer formation by using the same material for both structures. This consolidation eliminates the need for separate material deposition and interface management, reducing structural complexity while achieving the electrical reliability benefits of a protruding via.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The via material serves multiple functions: it provides electrical connection, forms the capping layer structure, and eliminates the need for additional barrier or seed layers at the via-capping layer interface. This multi-functionality reduces device complexity while maintaining improved electrical reliability through the protruding via structure.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP4629285A1Semiconductor device
Publication Date: 2025.10.08 SAMSUNG ELECTRONICS CO LTD
  • EP4629285A1 patent drawingFigure 1
  • EP4629285A1 patent drawingFigure 2
  • EP4629285A1 patent drawingFigure 3~4

AI summary

A semiconductor device includes a substrate, a first interlayer insulating layer, a lower wiring layer, a lower wiring capping layer, an etching stop layer, a second interlayer insulating layer, a via trench that extends into the etching stop layer and the second interlayer insulating layer in a first direction, and a via in the via trench, where the via is in contact with the upper surface of the lower wiring capping layer, where an upper surface of the via in the first direction relative to the upper surface of the substrate is higher than an upper surface of the second interlayer insulating layer in the first direction relative to the upper surface of the substrate, and where the lower wiring capping layer includes a same material as the via.