Via Critical Dimension Control via Two-Step Silicon ARC Etch
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Solution Overview
Problem
The challenge in modern microstructure fabrication, such as integrated circuits, lies in achieving precise and reliable patterning of low-k dielectric materials for via openings and metal lines, particularly at deep sub-micron scales, due to the complexity of copper diffusion and the need for high aspect ratio filling, which results in significant process variability and increased reworking, affecting electrical performance and throughput.
Innovation Solution
Implementing a two-step etch process with controlled gas flow rates for patterning a silicon-containing ARC layer, allowing for efficient adaptation and adjustment of via opening dimensions, thereby reducing the spread of critical dimensions and increasing the valid range of lithography results, and using this layer as a mask for the hard mask material to enhance process control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-step etch process is used for patterning the ARC layer, then the process is simple and fast, but the critical dimension control is poor and reworking increases
Solution Approach 1:
The etch process is divided into two distinct steps: a first etch step that etches a first portion of the ARC layer, and a second etch step that etches a second portion. This segmentation allows independent optimization of each step's parameters, enabling both high productivity and precise critical dimension control through selective gas flow rate adjustments in each step.
Solution Approach 2:
The etch process uses dynamic adjustment of gas flow rates between the two etching steps. By controlling the flow rate of the first gas component in the first step and the flow rate of the second gas component in the second step, the process adapts to achieve optimal etching profiles and critical dimensions, resolving the contradiction between speed and precision.
2Device complexity
If the lateral size of via openings is not controlled, then the lithography process is simple, but the spread of critical dimensions increases and electrical performance deteriorates
Solution Approach 1:
The lateral size of the via openings is controlled during the etching of the ARC layer itself, rather than relying solely on lithography. By adjusting gas flow rates during the two-step etch process, the critical dimensions are predetermined and controlled at the etching stage, reducing the spread of critical dimensions without significantly increasing overall process complexity.
3Reliability
If copper is used in the metallization system, then the electrical resistivity is reduced and electromigration resistance is improved, but copper diffusion in dielectric materials becomes a severe problem
Solution Approach 1:
An anti-reflective coating (ARC) layer is introduced as an intermediary between the copper metallization and the underlying dielectric materials. This ARC layer serves as a diffusion barrier, preventing copper from diffusing into the dielectric while also providing optical properties for lithography. The two-step etch process selectively patterns this intermediary layer to control via opening dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the spread of critical dimensions, decreases reworking, and enhances process robustness, allowing for a wider range of valid dimensions and improved electrical performance by efficiently controlling the lateral size of via openings, thus improving manufacturing efficiency and reducing maintenance needs.
Implementation Method 1
performing a first etch process by using an oxygen-containing precursor gas and a carbon and fluorine-containing precursor gas so as to form a first portion of an opening in a silicon-containing ARC layer
Implementation Method 2
performing a first etch process by using an oxygen-containing precursor gas and a carbon and fluorine-containing precursor gas
Implementation Method 3
performing a second etch process by using a polymerizing precursor gas so as to form the opening in the silicon-containing ARC layer through the first portion
Data Source
AI summary
When forming via openings in sophisticated semiconductor devices, a silicon-containing anti-reflective coating (ARC) layer may be efficiently used for adjusting the critical dimension of the via openings by using a two-step etch process in which, in at least one of the process steps, the flow rate of a reactive gas component may be controlled to increase or reduce the resulting width of an opening in the silicon ARC layer. In this manner, the spread of critical dimensions of vias around the target value may be significantly reduced while also reducing any maintenance and rework efforts.