Through-Chip Via Chip Identification for Stacked Semiconductor Devices
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Solution Overview
Problem
In three-dimensional stacked semiconductor devices using through-silicon vias, identifying individual slave chips is challenging due to the lack of an edge region for forming pads, leading to increased costs and form factor disadvantages, especially when using wire bonding structures.
Innovation Solution
A method employing a master chip that generates counter codes and transmits them through a through-chip via, allowing slave chips to latch and compare these codes for identification, using a combination of series and parallel transmission lines to uniquely identify each slave chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonding structure is used to connect stacked semiconductor chips, then chips can be interconnected, but form factor increases and fabrication cost increases
Solution Approach 1:
The patent extracts the identification function from the edge pad structure and implements it through through-chip vias. Instead of using edge pads for both connection and identification, the invention uses internal via holes to carry identification signals, separating the connection function (edge pads) from the identification function (via holes). This eliminates the need for additional interposer layers and reduces form factor while maintaining manufacturability.
Solution Approach 2:
The patent transitions from two-dimensional edge pad identification to three-dimensional through-chip via identification. By routing identification signals through vertical via holes penetrating the substrate, the invention utilizes the vertical dimension to carry identification information without increasing the horizontal footprint. This dimensional transition resolves the form factor issue while enabling chip identification.
2Measurement precision
If edge pads are used for chip identification in stacked packages, then chips can be identified, but wire bonding complexity increases and signal integrity deteriorates
Solution Approach 1:
The patent extracts the identification signal transmission path from the wire bonding route and relocates it through the substrate via holes. By routing identification signals through the substrate's via holes rather than through wire bonds, the invention eliminates the complexity of wire bonding for identification purposes while maintaining signal integrity through a more direct and stable transmission path.
Solution Approach 2:
The patent introduces the substrate's via holes as an intermediary transmission medium for identification signals. Instead of directly bonding wires to edge pads for identification, the invention uses the via holes as an intermediate pathway that carries identification signals through the substrate, simplifying the overall bonding structure and improving signal integrity.
3Area of stationary object
If through-chip vias are used to connect stacked chips, then form factor is reduced, but chip identification becomes difficult without edge regions
Solution Approach 1:
The patent makes the through-chip vias multi-functional by using them for both electrical connection and chip identification. The same via holes that provide vertical interconnection also serve as transmission pathways for identification signals. This universal usage of vias resolves the identification difficulty while maintaining the form factor advantage of through-chip via stacking.
Solution Approach 2:
The patent uses the vertical dimension of through-chip vias to carry identification signals, transforming the identification problem from a horizontal edge-pad issue to a vertical via-based solution. By routing identification signals through the vertical via holes, the invention enables chip identification without requiring horizontal edge regions, thus resolving the identification difficulty while preserving compact form factor.
4Reliability
If gold wire bonding is used to connect pads, then chips can be connected, but hetero-metal junction causes signal skew and increased power consumption
Solution Approach 1:
The patent extracts the identification signal transmission function from the gold wire bonding path and implements it through substrate via holes. By separating the identification function from the wire bonding structure, the invention eliminates the hetero-metal junction problem at identification interfaces, reducing signal skew and power consumption while maintaining connection reliability through the via structure.
Solution Approach 2:
The patent replaces the mechanical wire bonding system with a substrate-integrated via hole system for identification signal transmission. Instead of using gold wire bonds to carry identification signals, the invention substitutes a substrate-based via hole pathway that eliminates hetero-metal junctions, thereby reducing signal skew and power consumption while maintaining reliable connections.
Data Source
AI summary
A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result.