Through-Substrate Via Formation Using Conductive Stop Layer

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Solution Overview

Problem

Existing methods for producing through-substrate vias in semiconductor devices are not compatible with the integration of CMOS components, as they fail to adequately protect the metal layers from exposure during etching and subsequent cleaning processes, leading to surface damage and potential corrosion.

Innovation Solution

A method involving the use of a stop layer of electrically conductive material, such as TiN or TaN, between the metal layer and the semiconductor body, which prevents the metal layer from being exposed during via opening formation, combined with a thin electrically conductive liner to ensure electrical connection and protect the metal surface from cleaning agents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a via opening is formed through the semiconductor substrate to expose the metal layer for connection, then electrical connection is achieved, but the metal layer surface is damaged and corroded during etching and cleaning processes

Engineering Contradiction:
Improveelectrical connectionVSAvoidmetal layer surface damage and corrosion
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A stop layer of electrically conductive material is introduced as an intermediary between the metal layer and the etching process. This stop layer protects the metal layer from direct exposure to etching and cleaning agents while still allowing the via opening to be formed through the substrate to establish electrical connection.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The stop layer is arranged in advance between the metal layer and the substrate before the via opening formation process. This preliminary protective action prevents surface damage to the metal layer during subsequent etching and cleaning operations that would otherwise occur when forming the via opening.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the metal layer is exposed during via opening formation to establish connection, then electrical connectivity is achieved, but cleaning agents damage the metal surface

Engineering Contradiction:
Improveelectrical connectivityVSAvoidcleaning agent damage to metal surface
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The stop layer serves as a protective intermediary that shields the metal layer from cleaning agents during the via opening formation process. This allows standard cleaning agents to be used without damaging the metal surface, while the via opening still achieves electrical connectivity through the substrate.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Stability of the object's composition

If a protective layer is added to prevent metal exposure during etching, then metal layer integrity is maintained, but the process complexity increases

Engineering Contradiction:
Improvemetal layer integrityVSAvoidprocess complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The stop layer performs multiple functions simultaneously: it protects the metal layer from etching and cleaning damage, provides a defined etch stop for precise via opening formation, and maintains electrical conductivity for signal transmission. This multi-functionality reduces the need for additional separate protective layers or process steps.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP2790211B1Method of producing a through-substrate via in a semiconductor device and semiconductor device comprising a through-substrate via
Publication Date: 2018.06.20 AUSTRIAMICROSYSTEMS AG
  • EP2790211B1 patent drawingFigure 1
  • EP2790211B1 patent drawingFigure 2~3
  • EP2790211B1 patent drawingFigure 4~5

AI summary

The method comprises the steps of arranging an intermetal dielectric (2) on or above a main surface (10) of a semiconductor body (1) and at least one metal layer (5, 5') in the intermetal dielectric, and forming a via opening (3) from a rear surface (11) towards the metal layer. A stop layer (4) of electrically conductive material is arranged at the metal layer between the metal layer and the semiconductor body, and the via opening is formed at least up to the stop layer but not into the metal layer. The semiconductor device has a stop layer (4) between a section (5) of the metal layer and a metallization (19) of a through-substrate via that is arranged in the via opening, and an electrically conductive liner (6, 6') between the metal layer and the semiconductor body.