Via-Configurable Logic Block Transistor Chain Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Structured ASICs face challenges in reducing non-recurring engineering costs and manufacturing time due to the complexity of customizing multiple metal layers in traditional ASIC design processes, which limits their scalability and efficiency compared to FPGAs and standard cell ASICs.
Innovation Solution
The implementation of a via-configurable logic block (VCLB) architecture in Structured ASICs using CMOS process technology, allowing configuration through serial/parallel transistor structures and varying voltage threshold transistors and drive strength, reduces the need for multiple customizable metal layers by enabling programmable via connections between transistors and external ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional ASIC design process customizes multiple metal layers, then manufacturing precision and device performance are improved, but device complexity and non-recurring engineering costs increase
Solution Approach 1:
The patent extracts the configurability function from multiple metal layers and concentrates it into a single via-configurable layer. This removes the complexity of customizing multiple metal layers while preserving the essential functionality of configurable interconnect, thereby reducing device complexity and NRE costs without sacrificing manufacturing precision.
Solution Approach 2:
The via-configurable layer serves multiple functions: it provides configurable interconnect, enables logic block customization, and supports both ASIC and FPGA-like functionality. This multi-functional approach allows a single layer to replace the roles previously distributed across multiple metal layers, reducing overall device complexity.
2Power
If traditional ASIC design process customizes multiple metal layers, then device performance is improved, but non-recurring engineering costs and manufacturing time increase
Solution Approach 1:
The patent performs preliminary configuration of logic blocks and interconnect at the mask level before fabrication. This allows performance optimization to be built into the device structure in advance, eliminating the need for time-consuming post-fabrication customization while maintaining high device performance.
Solution Approach 2:
The patent uses standard cell libraries and pre-designed logic block templates that can be rapidly instantiated and configured. This copying approach allows performance-optimized designs to be replicated efficiently without requiring lengthy customization processes, thereby reducing manufacturing time while preserving device performance.
3Adaptability or versatility
If via-configurable logic block uses transistor chains with varying voltage thresholds, then adaptability and flexibility are improved, but device complexity increases
Solution Approach 1:
The patent applies different voltage threshold characteristics to specific transistor chains based on their functional requirements. By localizing the quality variations to where they are most needed in the logic blocks, the design achieves high adaptability without requiring complex configurations throughout the entire device, thereby controlling overall device complexity.
Data Source
AI summary
A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner.