Metal-Surrounded Via Contact for Precise Contact Opening Etching
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Solution Overview
Problem
Current semiconductor device manufacturing processes face challenges in achieving precise control over the etching of metal oxides and nitrides, particularly in the removal of residues during the formation of contact openings, which can lead to dimensional inaccuracies and profile changes in the semiconductor structure.
Innovation Solution
The use of metal halides, such as WF6, for etching metal oxides and nitrides, allowing for controlled etching rates and minimizing the impact on surrounding materials, thereby maintaining the structural integrity and profile of the contact openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to remove metal oxide residues, then the residues can be removed, but the contact opening dimensions and profiles are altered due to lack of etching control
Solution Approach 1:
The patent changes the chemical parameters of the etching process by using metal halide-based etchants (such as WF6, MoF6, RuF6, TiF4) instead of conventional etchants. This parameter change enables selective etching of metal oxides and nitrides while maintaining control over etching rates, thereby preserving contact opening dimensions and profiles while reliably removing residues.
Solution Approach 2:
The patent introduces metal halide compounds as intermediary substances that facilitate selective removal of metal oxide residues. These intermediaries react specifically with metal oxides to form volatile products, enabling precise residue removal without affecting the underlying semiconductor structure or contact opening geometry.
2Reliability
If aggressive etching is used to ensure complete residue removal, then residues are removed effectively, but the surrounding materials and structural profiles are damaged
Solution Approach 1:
The patent applies local quality by using etchants with selective chemical reactivity. The metal halide etchants are designed to react preferentially with metal oxides and nitrides at specific locations (residue areas) while having minimal interaction with surrounding materials. This localized selective etching ensures complete residue removal while preserving the integrity and profile accuracy of adjacent semiconductor structures.
Solution Approach 2:
The patent modifies the chemical reactivity parameters of the etching process by employing metal halide-based etchants that exhibit controlled reaction rates and selectivity. These etchants provide aggressive enough action to remove residues completely but with sufficient control to prevent damage to surrounding materials, thus resolving the contradiction between removal effectiveness and profile preservation.
3Ease of manufacture
If conventional etchants are used for residue removal, then the process is simple, but dimensional inaccuracies occur in the semiconductor structure
Solution Approach 1:
The patent changes the chemical composition parameters of the etching process from conventional etchants to metal halide-based etchants. This parameter change maintains process simplicity (single-step etching) while dramatically improving dimensional accuracy through selective reactivity and controlled etching rates that preserve contact opening dimensions and prevent structural distortion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient removal of residues while preserving the dimensions and profiles of the contact openings, contributing to the fabrication of semiconductor devices with improved precision and reliability.
Implementation Method 1
The use of metal halides, such as WF6, for etching metal oxides and nitrides, allowing for controlled etching rates and minimizing the impact on surrounding materials
Data Source
AI summary
A semiconductor device includes a substrate, a source/drain region disposed in the substrate, a silicide structure disposed on the source/drain region, a first dielectric layer disposed over the substrate, a conductive contact disposed in the first dielectric layer and over the silicide structure, a second dielectric layer disposed over the first dielectric layer, a via contact disposed in the second dielectric layer and connected to the conductive contact, and a first metal surrounding the via contact.