Via Contact Alignment via Patterned Conductive Mask
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Lithographic errors such as via misalignment and develop critical dimension issues in the formation of via contacts in integrated circuits can lead to electrical shorts between via contacts and underlying conductive lines, causing IC malfunction and reliability issues.
Innovation Solution
A method of forming semiconductor devices with via contacts that are precisely aligned within the underlying contact regions, using a patterned conductive mask layer that self-aligns with the contact regions, ensuring that via contacts do not extend beyond or displace from the underlying conductive lines, thereby preventing electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional lithographic alignment methods are used, then manufacturing process is simpler, but via contacts may misalign with underlying conductive lines causing electrical shorts
Solution Approach 1:
The patent applies preliminary action by forming a patterned conductive mask layer over the contact regions before forming the via contacts. This mask layer is prepared in advance with patterns that pre-compensate for lithographic errors, ensuring that when via contacts are subsequently formed, they automatically align with the underlying conductive lines even when lithographic errors occur. The mask layer serves as a preliminary alignment reference that prevents misalignment issues.
Solution Approach 2:
The patterned conductive mask layer acts as an intermediary element between the lithographic patterning process and the via contact formation. It mediates the alignment relationship by providing a physical reference structure that the via contacts align to, rather than relying directly on lithographic overlay between different layers. This intermediary mask layer absorbs and compensates for lithographic errors, preventing them from causing misalignment.
2Manufacturing precision
If tight overlay control is implemented to prevent misalignment, then via contact alignment improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies self-service by designing a process where the patterned conductive mask layer automatically provides alignment reference for the via contacts without requiring external tight overlay control. The mask layer's pattern is designed to self-align with the contact regions, and the via contacts self-align to the mask pattern through standard lithographic processes. This self-aligning mechanism eliminates the need for complex tight overlay control systems.
Solution Approach 2:
By preparing the patterned conductive mask layer in advance with pre-calculated pattern dimensions and positions that account for expected lithographic errors, the system performs preliminary alignment compensation. This preliminary action embeds the alignment solution into the mask layer design itself, eliminating the need for complex real-time overlay control during manufacturing.
3Reliability
If via contact size is increased to ensure coverage, then contact reliability improves, but risk of extending beyond conductive lines and causing shorts increases
Solution Approach 1:
The patent applies local quality by creating a patterned conductive mask layer with spatially varying patterns corresponding to different contact regions. Each area of the mask layer has locally optimized patterns that ensure via contacts are sized appropriately for their specific contact region while being constrained to align with underlying conductive lines. This local optimization allows via contacts to be large enough for reliable contact while preventing them from extending beyond conductive lines in any given location.
Solution Approach 2:
The patterned conductive mask layer serves as an intermediary that controls the size and position of via contacts. It mediates between the desire for large via contacts (for reliability) and the need to prevent them from extending beyond conductive lines (to avoid shorts). The mask layer's pattern design ensures that via contacts achieve sufficient size for reliable electrical connection while being geometrically constrained to remain within conductive line boundaries.
Data Source
AI summary
Semiconductor devices and methods of making thereof are disclosed. The semiconductor device includes a substrate prepared with a first dielectric layer formed thereon. The dielectric layer includes at least first, second and third contact regions. A second dielectric layer is disposed over the first dielectric layer. The device also includes at least first, second and third via contacts disposed in the second dielectric layer. The via contacts are coupled to the respective underlying contact regions and the via contacts do not extend beyond the underlying contact regions.