Self-Aligned Via Contact Etch for Semiconductor Wiring Overlay
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Solution Overview
Problem
The dual damascene process in semiconductor device fabrication faces challenges with overlay errors between via contacts and metal wiring layers, leading to issues like high electrical resistance or short circuits, especially as critical dimensions decrease.
Innovation Solution
A self-aligned process is introduced where via contacts are formed using a metal etching process that aligns with the metal wiring patterns above them, reducing overlay errors and improving alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dual damascene process is used to form via contact and metal wiring, then wiring layer formation is achieved, but overlay errors occur between via contacts and metal wiring layers leading to high electrical resistance or short circuits
Solution Approach 1:
The patent applies preliminary action by forming the via contact opening and filling it with conductive material before forming the metal wiring pattern. This sequence ensures that the via contact is already in place and can serve as a precise alignment reference for the subsequent metal wiring formation process, thereby reducing overlay errors and improving alignment accuracy between the via contact and metal wiring layer.
Solution Approach 2:
The patent introduces an intermediary approach by using a separate via contact formation process as a mediator between the substrate and the metal wiring layer. This intermediary via contact structure serves as a stable reference that decouples the alignment requirements, allowing the metal wiring to be formed with precise alignment to the via contact without directly compromising the reliability of the electrical connection.
2Area of moving object
If critical dimensions are decreased to achieve higher device density, then device integration is improved, but overlay errors increase leading to more electrical shorts or high resistance
Solution Approach 1:
The patent applies preliminary action by completing the via contact formation process before metal wiring patterning. This allows the via contact to serve as a stable, pre-formed alignment reference that is less sensitive to dimensional variations, enabling better alignment accuracy even when critical dimensions are decreased for higher device density.
Solution Approach 2:
The via contact structure serves itself as an alignment reference for the metal wiring formation process. By using the via contact's own position and dimensions as the reference, the process becomes self-aligning, which reduces sensitivity to overlay errors and maintains manufacturing precision even at smaller critical dimensions.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a first conductive pattern and a second conductive pattern are formed over the first conductive pattern, in a first interlayer dielectric (ILD) layer disposed over a substrate. The second conductive pattern contacts the first conductive pattern. A space is formed in the first ILD layer by removing a part of the second conductive pattern to expose a part of the first conductive pattern. The space is filled with a dielectric material. A third conductive pattern is formed over a remaining portion of the second conductive pattern. A via contact connecting the first conductive pattern and the third conductive pattern is formed by patterning the remaining portion of the second conductive pattern as an etching mask.