Via Contact Patterning Using Protective Helmet for Edge Placement Error Margin
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Solution Overview
Problem
As semiconductor features continue to scale down, the challenge of maintaining precise edge placement and preventing shorting between via contacts and underlying electrically conductive structures becomes increasingly difficult due to the limitations of etch selectivity and metal recess variability, especially at pitches below 70 nanometers and critical dimensions below 35 nanometers.
Innovation Solution
A via contact patterning method that involves creating a pattern of alternating trench contacts and gates with dielectric insulation, using a protective 'helmet' material to protect taller trench contacts during the patterning process, and employing vertical separation to prevent shorting, thereby increasing the edge placement error margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is scaled down to increase device density, then device capacity increases, but manufacturing precision deteriorates due to etch selectivity limitations and metal recess variability
Solution Approach 1:
The patent introduces vertical separation between via contacts and underlying electrically conductive structures, creating a height difference that provides a margin of error for edge placement. This dimensional approach (adding height/depth dimension) allows lateral alignment errors to be tolerated while maintaining electrical connectivity, thus resolving the contradiction between high device density and manufacturing precision at scaled dimensions
Solution Approach 2:
The patent employs dielectric materials as intermediary layers between via contacts and underlying electrically conductive structures. These dielectric layers act as buffers that accommodate alignment variations and prevent shorting, enabling precise via placement even when edge placement error occurs due to scaling limitations
2Quantity of substance
If via contact dimensions are reduced to increase device capacity, then device performance improves, but reliability deteriorates due to increased risk of shorting and edge placement errors
Solution Approach 1:
By creating vertical separation (height difference) between via contacts and underlying structures, the patent adds a dimensional buffer that prevents shorting even when lateral alignment is imperfect. This enables reliable via operation at reduced dimensions where traditional planar approaches would fail
Solution Approach 2:
The patent incorporates dielectric materials and vertical spacing as preventive measures before shorting can occur. This beforehand cushioning approach ensures that even with edge placement errors, the via contacts remain electrically isolated from underlying structures, maintaining reliability at scaled dimensions
Data Source
AI summary
An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.