Via Contact Structure for Low-Resistance Semiconductor Wiring
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Solution Overview
Problem
As semiconductor elements become more highly integrated, the resistance between wiring and vias increases, affecting the reliability of semiconductor devices.
Innovation Solution
A protective layer is formed on the upper surface of the via during the process of forming an upper wiring pattern, preventing the formation of an upper wiring barrier layer on the via, thereby reducing contact resistance between the upper wiring pattern and the via.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an upper wiring barrier layer is formed on the via to protect the wiring, then the wiring structure is more robust, but the contact resistance between the upper wiring pattern and the via increases
Solution Approach 1:
The patent applies local quality by making the barrier layer selectively present only in certain areas. The upper wiring barrier layer is formed on the side wall of the via trench but intentionally omitted from the upper surface of the via. This localized approach allows the barrier layer to provide protection where needed (side walls) while avoiding contact resistance issues at the critical contact interface (upper surface).
Solution Approach 2:
The barrier layer structure is segmented into different portions with different functions. The side wall portion of the upper wiring barrier layer provides structural protection and adhesion, while the upper surface of the via remains barrier-free to ensure low-resistance electrical contact. This segmentation resolves the contradiction by dividing the via interface into functional zones.
2Productivity
If the wiring components are downscaled to increase integration, then the chip uses less power and has higher integration, but the resistance between wiring and via increases
Solution Approach 1:
In the context of downscaled wiring components, the patent applies local quality by selectively removing the barrier layer only from the via upper surface contact region. This allows the overall integrated structure to maintain high density while the local contact interface maintains low resistance, solving the problem of increased resistance that typically accompanies scaling.
3Object-affected harmful factors
If a protective layer is formed on the via to prevent barrier layer formation, then contact resistance is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies preliminary action by forming a protective layer on the via upper surface before forming the upper wiring barrier layer. This preliminary protective layer prevents barrier material deposition on the via surface, ensuring low contact resistance. The protective layer is subsequently removed after serving its purpose, adding minimal steps to the overall process while achieving the desired low-resistance contact.
Data Source
AI summary
A semiconductor device includes a substrate, a first interlayer insulating layer on the substrate, a lower wiring pattern inside the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer, a second interlayer insulating layer on the etch stop layer, a via trench inside the second interlayer insulating layer and the etch stop layer and that extends to the lower wiring pattern, a via inside the via trench and that is in contact with the second interlayer insulating layer and is formed of a single film, an upper wiring trench formed inside the second interlayer insulating layer on the via, and an upper wiring pattern inside the upper wiring trench and that includes an upper wiring barrier layer and an upper wiring filling layer on the upper wiring barrier layer An upper surface of the via is in contact with the upper wiring filling layer.