Through-Substrate Via Crack Detection in Stacked Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in stacking semiconductor memory chips with penetrating electrodes is the electrical short-circuiting of electrodes at the same plane position, which limits the increase in connected electrodes, and the uneven bonding strength due to warping, leading to potential detachment of bump electrodes and reduced reliability.
Innovation Solution
A semiconductor device with through-substrate vias, a multi-level wiring structure, and crack check circuits that detect cracks in the wiring, allowing for accurate positioning and enhanced mechanical strength, and using a check line to determine the integrity of the wiring structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If accurate positioning is performed to ensure bump electrode contact during stacking, then bonding reliability can be improved, but the complexity of the stacking device increases
Solution Approach 1:
The substrate is pre-formed with multiple electrode forming areas and penetrating electrodes before chip stacking. This preliminary preparation establishes fixed, predetermined bonding positions that guide the stacking process, ensuring accurate bump electrode contact without requiring complex real-time positioning adjustments during stacking.
2Quantity of substance
If semiconductor chips are stacked with penetrating electrodes, then memory capacity can be increased, but uneven bonding strength due to warping may cause bump electrodes to detach
Solution Approach 1:
Each electrode forming area on the substrate is designed as an independent local region with its own penetrating electrodes and bonding structures. This local quality approach allows each area to independently accommodate and compensate for warping in the stacked chips, ensuring uniform bonding strength across all bump electrodes even when chips exhibit warpage, thereby preventing detachment.
Data Source
AI summary
Disclosed herein is a device that includes a semiconductor substrate, a check circuit and a through-substrate via. The check circuit includes a check line formed over the semiconductor substrate and including first and second parts each extending in a first direction and a third part extending in a second direction that crosses the first direction, the first and second parts being opposite to each other, the third part connecting one end of the first part with one end of the second part, a charge circuit coupled to a one end of the check line, and a comparator coupled to the other end of the check line at a first input node thereof. The through-substrate via penetrates through the semiconductor substrate and is located in an area that is between the first and second parts of the check line.