Via Defect Detection Using Fuse-Based Diode Arrays
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Solution Overview
Problem
The complexity of modern integrated circuits requires more vias for interconnects, making them prone to defects, and existing monitoring methods are inefficient in pinpointing failure locations due to the sheer size and complexity of the devices, limiting the ability to produce reliable and consistent vertical interconnects.
Innovation Solution
A system using a two-dimensional array of diodes and associated stacks of vertical interconnects and metal contacts, where each diode is addressable and connected in a grid, allowing for parallel testing of multiple chips with a tester that measures current through the stacks to identify anomalies and determine the location of defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If transistors are used as switches to enable individual via testing in a two-dimensional array, then via monitoring capability is improved, but transistor area consumption increases and current carrying capacity becomes limited
Solution Approach 1:
The patent extracts the switching function from traditional transistors and implements it using fuse-based selection mechanisms. Fuses are used to selectively connect or disconnect via stacks from test circuits, eliminating the need for transistor switches and their associated area and current limitations.
Solution Approach 2:
The patent employs fuses as disposable, non-reconfigurable switching elements. Once a fuse is blown to select a particular via stack for testing, it remains in that state. This approach is more area-efficient and current-capable compared to reusable transistor switches, accepting the trade-off of non-reconfigurability.
2Measurement precision
If transistors are used as switches for via testing, then individual via measurement capability is improved, but current carrying capacity is limited
Solution Approach 1:
The patent removes the switching function from transistors and assigns it to fuse-based selection mechanisms. This extraction allows high-current test signals to be applied to via stacks without being constrained by transistor current capacity, as fuses can handle the required test currents.
Solution Approach 2:
Fuses serve as high-current capable switching elements that can be permanently set to connect or disconnect via stacks. Their disposable nature allows them to be designed with high current carrying capacity without concern for repeated switching cycles, overcoming the current limitations of transistor-based approaches.
3Reliability
If large integrated circuits are used for monitoring process health, then process monitoring capability is improved, but failure location identification becomes difficult
Solution Approach 1:
The patent segments the test structure into multiple independent via stacks, each associated with specific addressable locations. By organizing vias into discrete, addressable stacks rather than testing entire large circuits, the system maintains process monitoring capability while enabling precise failure location identification through selective addressing of individual stacks.
Solution Approach 2:
The patent transitions from monolithic circuit-level testing to a two-dimensional array of addressable via stacks. This dimensional organization allows systematic addressing and isolation of specific via locations, converting the undifferentiated failure analysis of large circuits into precise spatial localization of defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for precise identification of defects in the manufacturing process, enabling more reliable and consistent via interconnects by analyzing current measurements and resistance calculations, thereby improving the yield and reliability of semiconductor fabrication.
Implementation Method 1
a system for process monitoring of semiconductor fabrication comprising a two-dimensional array of diodes and associated stacks of vertical interconnects and metal contacts, wherein each diode is addressable and connected in a grid
Data Source
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AI summary
A method for monitoring a semiconductor fabrication process creates a wafer of semiconductor chips. Each chip has a one or more diodes. Each diode is addressable as part of an array, corresponds to a physical location of the chip, and is connected in series to a stack. The stack is composed of one ore more vertical interconnects and metal contacts. The diode and associated stack of vertical interconnects is addressed, and the current through each of the stacks of vertical interconnects in an array is measured.