Via Defect Modeling for MEOL/BEOL Fault Localization
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Solution Overview
Problem
Conventional physical failure analysis methods struggle to identify and locate defects in Middle-End-of-Line (MEOL)/Back-End-of-Line (BEOL) layers of semiconductor circuits due to the absence of hot spots of electron hole combinations, making it difficult to diagnose and isolate defects, especially those causing high resistance in vias.
Innovation Solution
A method is developed to model MEOL/BEOL defects based on vias by extracting via information from standard cell layouts, simulating abnormal resistance values, and generating test patterns to detect defects using Automatic Test Pattern Generation (ATPG), facilitating accurate identification and localization of via defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional physical failure analysis methods are used, then the analysis process is simple, but the ability to identify and locate defects in MEOL/BEOL layers is insufficient
Solution Approach 1:
The patent introduces an intermediary computational model that simulates electron-hole recombination hot spots. This virtual mediator allows indirect detection of defects in MEOL/BEOL layers by modeling their effect on carrier recombination, enabling defect identification without direct physical observation methods.
Solution Approach 2:
The patent replaces conventional mechanical/physical failure analysis methods with a computational simulation approach. By using computer-based modeling of electron-hole recombination phenomena, the system substitutes physical inspection techniques with virtual simulation and data comparison methods.
2Reliability
If sophisticated testing methods are implemented, then defect detection capability improves, but testing complexity and cost increase
Solution Approach 1:
The patent performs preliminary computational modeling and simulation before actual physical testing. By pre-calculating expected hot spot patterns for various defect scenarios, the system prepares reference data that guides subsequent testing and analysis, reducing the complexity of real-time defect identification.
Solution Approach 2:
The patent creates virtual copies of defect scenarios through computational modeling. By simulating various defect conditions and their corresponding hot spot patterns in a virtual environment, the system generates reference models that can be compared against actual measurements without requiring physical defect samples.
3Measurement precision
If via defects with high resistance are targeted, then specific defect types are identified, but detection difficulty increases due to absence of hot spots
Solution Approach 1:
The patent changes the detection parameter from direct electrical resistance measurement to computational modeling of electron-hole recombination dynamics. By modeling how via defects affect carrier transport and recombination rates, the system transforms an difficult-to-detect high-resistance defect into a detectable perturbation in hot spot patterns.
Data Source
AI summary
A method includes acquiring a design layout of a standard cell, extracting feature information of one or more vias in the standard cell from the design layout, performing a circuit simulation to obtain first simulation outputs of the standard cell for input patterns by applying a first abnormal resistance value as a parasitic resistance value of a first via among the one or more vias, the first abnormal resistance value being different from a nominal parasitic resistance value of the first via, determining whether the first simulation outputs match corresponding expected outputs of the standard cell for the input patterns, and in response to one or more simulation outputs among the first simulation outputs not matching the corresponding expected outputs, recording one or more defect types for the first via having the first abnormal resistance value along with corresponding input patterns and corresponding simulation outputs.