Via Definition Scheme Single Mask Integration

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Solution Overview

Problem

Current integrated circuit fabrication processes require two separate masks and exposure processes to define metal lines and vias, making them inefficient and costly.

Innovation Solution

A via definition scheme that uses a single photolithography exposure of a metal pattern layer and a spacer layer to form a metal trench and via hole, reducing the need for multiple masks and exposures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If two separate masks and exposure processes are used to define metal lines and vias, then the definition precision of metal lines and vias is improved, but the device complexity and manufacturing cost increase

Engineering Contradiction:
Improvedefinition precision of metal lines and viasVSAvoidcomplexity of mask and exposure processes
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines the definition of metal lines and vias into a single exposure process by using a metal pattern layer with variable width features. The wider portions of the metal pattern define via locations while narrower portions define metal line regions, allowing both features to be defined simultaneously in one exposure step rather than requiring separate masks.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The metal pattern layer serves multiple functions: it defines both metal line regions and via locations, acts as an etch mask for forming both metal trenches and via holes, and eliminates the need for separate via definition masks. This multi-functionality reduces process complexity while maintaining definition precision.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If two separate masks and exposure processes are used to define metal lines and vias, then the definition precision of metal lines and vias is improved, but the manufacturing cost increases

Engineering Contradiction:
Improvedefinition precision of metal lines and viasVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent combines the definition of metal lines and vias into a single exposure process by using a metal pattern layer with variable width features. The wider portions of the metal pattern define via locations while narrower portions define metal line regions, allowing both features to be defined simultaneously in one exposure step rather than requiring separate masks.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The metal pattern layer serves multiple functions: it defines both metal line regions and via locations, acts as an etch mask for forming both metal trenches and via holes, and eliminates the need for separate via definition masks. This multi-functionality reduces process complexity while maintaining definition precision.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If two separate masks and exposure processes are used to define metal lines and vias, then the definition precision of metal lines and vias is improved, but the productivity decreases

Engineering Contradiction:
Improvedefinition precision of metal lines and viasVSAvoidfabrication efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent combines the definition of metal lines and vias into a single exposure process by using a metal pattern layer with variable width features. The wider portions of the metal pattern define via locations while narrower portions define metal line regions, allowing both features to be defined simultaneously in one exposure step rather than requiring separate masks.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The metal pattern layer serves multiple functions: it defines both metal line regions and via locations, acts as an etch mask for forming both metal trenches and via holes, and eliminates the need for separate via definition masks. This multi-functionality reduces process complexity while maintaining definition precision.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9748133B2Via definition scheme
Publication Date: 2017.08.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9748133B2 patent drawing
  • US9748133B2 patent drawing
  • US9748133B2 patent drawing

AI summary

A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer.