Via Placement on Edge Regions for MPL Color Conflict Resolution
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Solution Overview
Problem
In integrated circuits, the shrinking gaps between adjacent patterns require multiple patterning lithography (MPL) techniques, but existing methods face challenges in ensuring adequate spacing between patterns to avoid color violations and optimize area usage, especially in multiple patterning lithography layers like quadruple patterning lithography (QPL) and triple patterning lithography (TPL).
Innovation Solution
The solution involves designing an integrated circuit with specific pattern widths and via placements, where the first and second lower patterns have greater widths than the vias, and the vias are positioned on edge regions of the patterns, allowing the first and second upper patterns to be adjacent with appropriate color assignments to maintain minimum spacing and prevent color conflicts, thereby optimizing the layout for MPL techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple patterning lithography is used to form patterns with smaller gaps, then the circuit density is improved, but the complexity of the manufacturing process increases due to color decomposition and multiple masks
Solution Approach 1:
The manufacturing process is segmented into multiple lithography steps, each forming a subset of the final pattern. By dividing the pattern formation into discrete stages (first pattern set, second pattern set, third pattern set), the complex task of creating dense circuits is broken down into manageable steps that can be executed with standard lithography tools, thus achieving high circuit density without requiring a single excessively complex process
Solution Approach 2:
The patent introduces a temporal dimension to the patterning process by using multiple lithography steps performed at different times. Instead of attempting to form all patterns in a single step, the process unfolds across multiple stages with intermediate steps (such as mandrel formation, spacer deposition, and pattern transfer), effectively adding a time dimension to resolve the complexity constraint
2Area of stationary object
If patterns are placed closer together to optimize area usage, then the area efficiency is improved, but the risk of color violations increases
Solution Approach 1:
The patent performs preliminary color decomposition and pattern assignment before final pattern placement. By pre-determining which patterns belong to which color groups and assigning them to specific lithography steps in advance, the method ensures that patterns requiring different colors are sufficiently separated, thus preventing color violations while allowing optimal area utilization in the final layout
Solution Approach 2:
The patent applies different spacing requirements to different regions of the layout based on color assignments. Patterns assigned to the same color group can be placed closer together, while patterns assigned to different color groups maintain larger separations. This localized quality control allows area optimization in regions where color conflicts are not possible, while maintaining reliability in regions where color violations must be prevented
3Quantity of substance
If via width is reduced to increase pattern density, then the circuit capacity is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent introduces spacers as intermediary structures between the mandrels and the final patterns. These spacers serve as a buffering layer that defines the final pattern dimensions with higher precision than direct lithography would allow. The spacer width, controlled by conformal deposition thickness, becomes the critical dimension rather than the mandrel width, enabling better control over via and pattern dimensions while increasing circuit capacity
Solution Approach 2:
The patent replaces direct optical lithography dimension control with a deposition-based dimensional control mechanism. Instead of relying on optical resolution to define via dimensions, the method uses atomic layer deposition or chemical vapor deposition to form spacers with precisely controlled thickness, substituting optical mechanics with vapor-phase deposition mechanics that offer superior dimensional control at the required scale
4Length of stationary object
If more color groups are used to reduce spacing constraints, then the pattern spacing is improved, but the number of lithography masks increases
Solution Approach 1:
The patent employs periodic repetition of the lithography-etch-deposition cycle across multiple stages. Each color group undergoes a similar sequence of operations (lithography to define mandrels, deposition to form spacers, etch to transfer patterns), but these operations are performed periodically across different time steps rather than simultaneously. This periodic action allows the use of a limited set of process steps repeated multiple times, managing mask complexity while achieving adequate spacing through temporal separation
Data Source
AI summary
An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.