Semiconductor Via-Epitaxy Layout for CMP Surface Flatness
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Solution Overview
Problem
In semiconductor devices, excessive steps in layers before Chemical Mechanical Polishing (CMP) result in poor flatness of the planarized surface, affecting device performance.
Innovation Solution
The semiconductor device design includes a substrate with a first and second active structure, an epitaxy, and a conductive via, where the conductive via is connected to the epitaxy and has a height less than 35 nanometers, improving the flatness of the planarized surface to less than 10 nanometers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If excessive steps are present in layers before CMP, then the structural complexity is increased, but the flatness of the CMP planarized surface deteriorates
Solution Approach 1:
The patent applies preliminary action by forming an etch stop layer and dummy patterns before the CMP process. These preliminary structures serve as reference planes that guide the CMP polishing process, ensuring that the final planarized surface achieves the required flatness even when underlying layers have significant steps or height variations.
Solution Approach 2:
The etch stop layer acts as an intermediary between the underlying active structures with excessive steps and the upper layers requiring planarization. This intermediate layer provides a stable base that enables uniform CMP polishing, mediating the transition from a non-planar to a planar surface while protecting the underlying structures.
2Manufacturing precision
If the height of conductive via is reduced to less than 35 nanometers, then the flatness of planarized surface is improved, but the resistance of conductive via is reduced
Solution Approach 1:
The patent applies parameter changes by precisely controlling the height of the conductive via to be less than 35 nanometers. This parameter optimization achieves a balance where the via height is sufficient to maintain electrical connectivity with acceptable resistance (reduced by 4% to 6% compared to taller vias) while being short enough to contribute to the overall flatness of the planarized surface, achieving less than 10 nanometers flatness.
Data Source
AI summary
A semiconductor device includes a substrate, a first active structure, a second active structure, an epitaxy and a conductive via. The first active structure is formed on the substrate and including a plurality of first sheets and a plurality of first spacers. The second active structure is disposed formed on the substrate and adjacent to the first active structure, wherein the second active structure includes a plurality of second sheets and a plurality of second spacers, the second sheets and the second spacers are stacked to each other, and there is trench between the first active structure and the second active structure. The epitaxy is formed within the trench. The conductive via is connected with the epitaxy. The semiconductor device further has a planarized surface including the first active structure, the second active structure and the conductive via, and the planarized surface has a flatness less than 10 nm.