Via Opening Etch Profile Control Using Oxidized MCESL Sidewalls

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Solution Overview

Problem

The challenge in integrated circuit fabrication is the risk of leakage current due to lateral etching during the formation of source/drain vias, which can lead to increased dimensions and bowing profiles, potentially affecting the integrity and performance of transistors like FinFETs and GAA devices.

Innovation Solution

An additional plasma treatment for the middle contact etch stop layer (MCESL) sidewall oxidation is introduced to create an oxidized region with different etch selectivity, slowing down lateral etching and reducing the risk of leakage current by inhibiting lateral etching during the liner removal process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etching process is used for via opening formation, then via openings can be formed, but lateral etching occurs causing increased dimensions and bowing profiles

Engineering Contradiction:
Improvevia opening profile controlVSAvoidlateral etching
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

An oxidized region is introduced as an intermediary layer between the MCESL and the etching process. This oxidized region acts as a mediator that modifies the etching behavior at the interface, preventing lateral etching while allowing vertical etching to proceed. The oxidized region is formed by plasma treatment of the MCESL sidewalls before the via opening etch, creating a protective barrier that controls the etch profile.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The chemical composition and physical properties of the MCESL sidewalls are changed through plasma oxidation treatment. This parameter change creates an oxidized region with different etch selectivity compared to the unoxidized MCESL, enabling precise control over the via opening profile by altering how the etchant interacts with the material at the critical interface region.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If etching duration is increased to ensure complete via opening, then leakage current risk increases due to lateral etching

Engineering Contradiction:
Improveleakage current preventionVSAvoidvia opening dimensions
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The oxidized region serves as a protective intermediary that allows the etching process to proceed to completion without excessive lateral etching. By modifying the MCESL sidewall properties through oxidation, the etchant is directed to etch vertically through the ILD layer while the oxidized region resists lateral attack, enabling complete via opening formation with controlled dimensions.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If plasma treatment for MCESL sidewall oxidation is applied, then lateral etching is inhibited, but process complexity increases

Engineering Contradiction:
Improvelateral etching controlVSAvoidetching process steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The MCESL sidewall oxidation is performed as a preliminary action before the via opening etch. By pre-modifying the MCESL sidewalls with plasma treatment to create the oxidized region, the subsequent etching process can proceed without additional complexity. This preliminary preparation enables the etch to self-align and self-regulate, reducing the need for complex real-time controls during the actual via formation.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces the risk of leakage current and alleviates bowing profiles in via openings, improving the structural integrity and performance of integrated circuit transistors by maintaining precise etching control and reducing RC delay.

Implementation Method 1

An additional plasma treatment for the middle contact etch stop layer (MCESL) sidewall oxidation is introduced to create an oxidized region with different etch selectivity

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

An additional plasma treatment for the middle contact etch stop layer (MCESL) sidewall oxidation is introduced

Methodology Applied
Scientific EffectPlasma treatment: Plasma

Data Source

PatentUS11749732B2Etch profile control of via opening
Publication Date: 2023.09.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11749732B2 patent drawing
  • US11749732B2 patent drawing
  • US11749732B2 patent drawing

AI summary

A method comprises forming a source/drain contact over a source/drain region; forming an etch stop layer over the source/drain contact and an interlayer dielectric (ILD) layer over the etch stop layer; performing a first etching process to form a via opening extending through the ILD layer and a recess in the etch stop layer; oxidizing a sidewall of the recess in the etch stop layer; after oxidizing the sidewall of the recess in the etch stop layer, performing a second etching process to extend the via opening down to the source/drain contact; and after performing the second etching process, forming a source/drain via in the via opening.