Via Etch PCM Structure for Monitoring Contact Landing Depth
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Solution Overview
Problem
In integrated circuits, the back-end-of-line processing for forming via contacts in metallization layers faces challenges due to etch tool parameter drift, leading to unlanded or insufficiently landed via contacts, which result in high resistance connections or open connections, impacting device performance and functionality, especially in high-frequency circuits where increased IMD layer thickness exacerbates the issue.
Innovation Solution
A process control monitoring structure is introduced, comprising a via chain capacitor that includes lower and upper PCM interconnects separated by dielectric, allowing for the measurement of via contact depth by applying a test voltage and measuring capacitance, thereby ensuring reliable via contact landing and preventing etch process drift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a timed etch is performed to form via openings, then the via opening can expose metal lines below, but etch tool parameter drift may result in insufficient landing or unlanded via contacts
Solution Approach 1:
The patent applies preliminary action by forming a process control monitoring structure before the actual via contact formation. This monitoring structure includes a test via opening and reference structures that allow measurement of etch depth and landing precision before production via contacts are formed. The measurement results are then used to adjust etch parameters to ensure proper landing.
Solution Approach 2:
The patent implements feedback by measuring the depth and landing of the process control monitoring structure's via opening, comparing it against target specifications, and using this information to adjust subsequent etch process parameters. This closed-loop feedback ensures that etch tool parameter drift is detected and corrected to maintain via contact landing precision.
2Reliability
If the thickness of IMD layers is increased for high frequency circuits, then signal integrity is improved, but the via opening process becomes more prone to unlanded via contacts
Solution Approach 1:
The patent applies preliminary action by forming a process control monitoring structure with a test via opening through the increased IMD layer thickness before actual via contacts are formed. This allows measurement of etch depth and landing precision specific to the thicker IMD configuration, enabling optimization of etch parameters for the specific IMD thickness being used.
Solution Approach 2:
The patent applies parameter changes by adjusting etch process parameters based on measurements from the process control monitoring structure. When IMD layer thickness is increased, the etch depth, time, and other parameters are optimized based on feedback from the monitoring structure to ensure proper via contact landing through the thicker dielectric.
3Reliability
If etch tool parameters drift over time, then process stability deteriorates, but continuous monitoring and adjustment are needed which increases process complexity
Solution Approach 1:
The patent implements feedback by continuously measuring the depth and landing of via openings using the process control monitoring structure and using this information to adjust etch parameters in real-time. This automated feedback loop detects parameter drift and corrects it without requiring complex manual monitoring, maintaining process stability through systematic control.
Solution Approach 2:
The patent applies self-service by designing the process control monitoring structure to automatically measure its own via opening characteristics and provide feedback for parameter adjustment. The structure includes built-in reference features and measurement capabilities that enable the process to self-diagnose and self-correct without external intervention, reducing the complexity of external monitoring systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively monitors and ensures sufficient via contact depth, preventing unlanded or insufficiently landed contacts, thereby maintaining device performance and functionality by adjusting etch processes to prevent over- or under-etching, thus enhancing the reliability of interconnects in integrated circuits.
Implementation Method 1
The PCM structure forms a via chain capacitor which is configured to generate a PCM capacitance indicating a depth of the via contacts of Vi with respect to metal lines of Mi when a PCM test voltage is applied to the PCM structure.
Data Source
AI summary
The present disclosure relates to a semiconductor device. The semiconductor device includes semiconductor substrate and a BEOL dielectric having x number of intermetal dielectric (IMD) layers, wherein an ith ILD layer, where i=1 to x, includes a metal dielectric layer Mi with metal lines, and a via dielectric layer Vi above the Mi, the via dielectric layer includes via contacts, the via contacts are coupled to metal lines of Mi and Mi+1. The semiconductor device also includes a process control monitoring (PCM) structure for monitoring via contact landing of via contacts of Vi landing on metal lines of Mi. The PCM structure includes a lower PCM interconnect disposed on Mi. The PCM structure also PCM via contacts, wherein the PCM via contacts are disposed proximately to the lower metal interconnect and extend below a top surface of the lower PCM interconnect by an overlap distance OV, the PCM via contacts are separated by dielectric of Mi. The PCM structure further includes an upper PCM interconnect disposed on Mi+1, wherein the upper interconnect is coupled to top surfaces of the PCM via contacts. The PCM structure forms a via chain capacitor which is configured to generate a PCM capacitance indicating a depth of the via contacts of Vi with respect to metal lines of Mi when a PCM test voltage is applied to the PCM structure.