Via Opening Etch Profile Control With Oxide Etch-Resistant Layer
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Solution Overview
Problem
The formation of tiger tooth-like recesses in gate dielectric caps during the etching process for via openings in integrated circuit fabrication leads to increased leakage current risk and non-vertical via profiles, which affect contact resistance and reliability.
Innovation Solution
Incorporation of an oxide-based layer with different etch selectivity on the gate dielectric caps to slow down the liner removal etching process, preventing excessive etching and maintaining a vertical via profile, thereby reducing leakage current risk and improving contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the liner removal etching process is performed without an oxide-based layer, then the etching speed is fast and productivity is high, but tiger tooth-like recesses form and via profile verticality deteriorates
Solution Approach 1:
An oxide-based layer is introduced as an intermediary between the liner layer and the gate dielectric cap. This intermediary layer modulates the etching process by providing selective protection, allowing the etch to proceed vertically through the liner while preventing lateral etching that causes tiger tooth recesses, thus maintaining via profile verticality without significantly compromising etching speed
Solution Approach 2:
The etching process parameters are changed by introducing the oxide-based layer which has different etch selectivity characteristics. The layer enables differential etching rates between vertical and lateral directions, transforming the etching behavior from isotropic (causing tiger teeth) to anisotropic (maintaining vertical profiles)
2Device complexity
If the liner removal etching process is performed without an oxide-based layer, then the process is simple and device complexity is low, but leakage current increases due to tiger tooth-like recesses
Solution Approach 1:
The oxide-based layer serves as a protective intermediary that prevents direct excessive etching of the gate dielectric cap. By mediating the etching interaction, it eliminates tiger tooth-like recesses that would otherwise create leakage paths, thereby improving device reliability with minimal added process complexity
Solution Approach 2:
The oxide-based layer is deposited beforehand to cushion and protect the gate dielectric cap during the liner removal etching process. This prior protection prevents the formation of harmful tiger tooth recesses before they can occur, ensuring reliable via profiles
3Loss of time
If the liner removal etching process is performed without an oxide-based layer, then the etching process is complete quickly and loss of time is reduced, but contact resistance increases due to non-vertical via profiles
Solution Approach 1:
The oxide-based layer acts as a temporal mediator during etching, providing just enough protection to maintain vertical via profiles without requiring excessive etching time. The selective etch properties allow the process to complete efficiently while ensuring proper via geometry for optimal contact resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The oxide-based layer controls the etching process, preventing tiger tooth-like recesses and enhancing the verticality of via openings, thus reducing leakage current and improving contact area and resistance.
Implementation Method 1
Incorporation of an oxide-based layer with different etch selectivity on the gate dielectric caps to slow down the liner removal etching process
Data Source
AI summary
A device includes source/drain epitaxial structures over a substrate, source/drain contacts over the source/drain epitaxial structures, respectively, a gate structure laterally between the source/drain contacts, a gate dielectric cap over the gate structure, an oxide-based etch-resistant layer over the gate dielectric cap, a nitride-based etch stop layer over the oxide-based etch-resistant layer, and an interlayer dielectric (ILD) layer over the nitride-based etch stop layer. The device further includes a via structure extending through the ILD layer, the nitride-based etch stop layer, and the oxide-based etch-resistant layer to electrically connect with the one of the source/drain contacts.


