Via Opening Etch Profile Control With Oxide Gate Cap Layer
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Solution Overview
Problem
The existing methods for forming integrated circuit structures, particularly in the fabrication of transistors like FinFETs and GAA devices, face challenges with excessive over-etching during the formation of source/drain vias, leading to a tiger tooth-like recess in the gate dielectric cap, which increases the risk of leakage current and contact resistance due to the lack of etch selectivity between nitride-based materials.
Innovation Solution
Incorporating an additional oxide-based layer on the gate dielectric caps with different etch selectivity than the nitride-based materials, which slows down the liner removal etching process, preventing the tiger tooth-like pattern and enhancing the vertical profile of via openings, thus reducing leakage current and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single nitride-based layer is used for gate dielectric cap, then the structure is simple, but excessive over-etching occurs during via formation
Solution Approach 1:
The gate dielectric cap is segmented into two distinct layers: a first nitride-based layer and a second oxide-based layer. This segmentation allows each layer to serve different functions during etching - the nitride layer provides etch selectivity to prevent over-etching, while the oxide layer enables controlled via formation, thereby resolving the contradiction between structural simplicity and via profile control precision.
Solution Approach 2:
The gate dielectric cap uses a composite structure combining nitride-based material and oxide-based material with different etch selectivities. This composite approach allows the etching process to selectively remove the oxide layer while preserving the nitride layer, preventing excessive over-etching and achieving precise via profile control without excessive complexity.
2Reliability
If high etch selectivity between nitride-based materials is used, then over-etching is prevented, but tiger tooth-like recess forms in gate dielectric cap
Solution Approach 1:
By segmenting the gate dielectric cap into a nitride-based layer and an oxide-based layer, the patent prevents the tiger tooth-like recess problem. The oxide layer acts as a sacrificial layer that can be selectively removed without affecting the nitride layer, allowing clean via formation without the lateral etching that causes tiger tooth patterns.
Solution Approach 2:
The oxide-based layer serves as an intermediary between the nitride-based layer and the via opening. It mediates the etching process by being selectively removed to form the via, while the nitride layer remains intact, preventing the tiger tooth-like recess formation that occurs when etching directly into nitride-based materials.
3Manufacturing precision
If additional oxide-based layer is added to gate dielectric cap, then via profile control improves, but device complexity increases
Solution Approach 1:
The patent changes the material parameter of the gate dielectric cap by introducing an oxide-based layer with different etch selectivity characteristics. This parameter change enables precise via profile control through selective etching, where the oxide layer is removed while the nitride layer remains, achieving the desired via geometry with minimal additional complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The oxide-based layer effectively slows down the etching process, preventing excessive over-etching and resulting in a more vertical via profile, reducing leakage current and decreasing contact resistance between source/drain vias and contacts.
Implementation Method 1
Incorporating an additional oxide-based layer on the gate dielectric caps with different etch selectivity than the nitride-based materials, which slows down the liner removal etching process
Data Source
AI summary
A method comprises forming a gate dielectric cap over a gate structure; forming source/drain contacts over the semiconductor substrate, with the gate dielectric cap laterally between the source/drain contacts; depositing an etch-resistant layer over the gate dielectric cap; depositing a contact etch stop layer over the etch-resistant layer and an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etching process to form a via opening extending through the ILD layer and terminating prior to reaching the etch-resistant layer; performing a second etching process to deepen the via opening such that one of the source/drain contacts is exposed, wherein the second etching process etches the etch-resistant layer at a slower etch rate than etching the contact etch stop layer; and depositing a metal material to fill the deepened via opening.