Source/Drain Via Etch Profile Control Using MCESL Sidewall Oxidation
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Solution Overview
Problem
The challenge in integrated circuit fabrication is the risk of leakage current due to lateral etching during the formation of source/drain vias, which can lead to increased dimensions of via openings and bowing profiles, potentially causing electrical leakage between source/drain and gate contacts.
Innovation Solution
An additional plasma treatment for the middle contact etch stop layer (MCESL) sidewall oxidation is implemented, creating an oxidized region with different etch selectivity that slows down lateral etching, thereby reducing the risk of leakage current and maintaining a bowing-free via opening profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching is used to form via openings, then via openings can be created, but lateral etching occurs causing increased dimensions and bowing profiles that lead to leakage current
Solution Approach 1:
The patent applies preliminary action by performing plasma treatment to oxidize the MCESL sidewalls before the via etching process. This oxidation creates a protective layer that prevents lateral etching during subsequent etching steps, thereby maintaining via opening profile precision and preventing leakage current before the problem can occur.
Solution Approach 2:
The patent introduces an intermediary substance (oxidized layer on MCESL sidewalls) that mediates between the etching process and the via opening walls. This oxidized layer acts as a protective intermediary that slows down lateral etching, allowing the via opening to maintain its intended dimensions and profile without direct harmful interaction with the etchant.
2Reliability
If etching parameters are adjusted to prevent lateral etching, then leakage current risk is reduced, but via opening formation time increases
Solution Approach 1:
The plasma treatment step performs preliminary oxidation of the MCESL sidewalls before etching, which enables faster etching parameters to be used subsequently without risking lateral etching. This preliminary preparation allows the process to maintain both high reliability and productivity, as the protective layer is already in place to prevent leakage while enabling more aggressive etching speeds.
3Manufacturing precision
If additional plasma treatment is added to oxidize MCESL sidewalls, then lateral etching is inhibited and via opening profile is maintained, but process complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the chemical state of the MCESL sidewalls through plasma oxidation, changing them from a non-oxidized to an oxidized state. This parameter change (oxidation state) fundamentally alters the etch resistance of the sidewalls, enabling precise via opening formation. The added step is justified by the significant improvement in via opening linearity and the prevention of leakage current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MCESL sidewall oxidation effectively inhibits lateral etching, reducing the risk of leakage current and ensuring a linear, bowing-free via opening, thus enhancing the electrical integrity and reducing RC delay in integrated circuits.
Implementation Method 1
An additional plasma treatment for the middle contact etch stop layer (MCESL) sidewall oxidation is implemented, creating an oxidized region with different etch selectivity
Data Source
AI summary
A device comprises a source/drain contact over a source/drain region of a transistor, an etch stop layer above the source/drain contact, an interlayer dielectric (ILD) layer above the etch stop layer, and a source/drain via extending through the ILD layer and the etch stop layer to the source/drain contact. The etch stop layer has an oxidized region in contact with the source/drain via and separated from the source/drain contact.