Through-Substrate Via Etch-Stop Layout to Reduce Cracks
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Solution Overview
Problem
Cracks and leakage currents occur in semiconductor devices due to differences in thermal expansion coefficients between metal layers and non-conductive materials in through silicon vias, leading to reduced efficiency and potential humidity ingress.
Innovation Solution
Incorporating an electrically conductive etch-stop layer with a larger lateral extent than the via, and smaller contact layers, arranged symmetrically and electrically connected, to mitigate thermal stress and reduce crack formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal layers with different coefficients of thermal expansion are arranged around and between non-conductive material in through silicon vias, then electrical connectivity is achieved, but cracks occur during processing leading to leakage currents and reduced device efficiency
Solution Approach 1:
An intermediate layer is introduced between the metal layers and non-conductive material in the through silicon via structure. This intermediate layer acts as a stress buffer that accommodates the differential thermal expansion between materials, preventing crack formation while maintaining electrical connectivity. The intermediate layer absorbs thermal stress during processing, eliminating the harmful cracks that would otherwise lead to leakage currents and device failure.
Solution Approach 2:
The patent modifies the physical and chemical parameters of the materials used in the via structure, specifically selecting materials with compatible thermal expansion coefficients or introducing gradient compositions. By changing material parameters to better match thermal expansion characteristics, the stress differential is reduced, preventing crack formation during thermal processing while maintaining the required electrical conductivity.
2Reliability
If through silicon vias are formed to electrically contact integrated circuits, then electrical connectivity is established, but thermal expansion differences cause cracks that lead to leakage currents and humidity ingress
Solution Approach 1:
The intermediate layer serves as a protective mediator that prevents the formation of cracks which would otherwise create pathways for leakage currents. By buffering the thermal stress, the intermediate layer maintains the integrity of the via structure, preventing the generation of harmful leakage currents while preserving the electrical connectivity function.
Solution Approach 2:
The intermediate layer is pre-positioned in the via structure before final assembly and processing. This layer provides advance cushioning against thermal expansion stresses that will occur during subsequent processing steps, preventing crack formation before it can lead to leakage currents or humidity ingress.
3Productivity
If multiple metal layers are stacked to provide electrical connections, then connectivity is improved, but thermal stress from coefficient differences increases crack risk
Solution Approach 1:
The intermediate layer is strategically positioned between metal layers with different thermal expansion coefficients. It acts as a stress-absorbing intermediary that allows each metal layer to expand and contract at its own rate during thermal processing, preventing the accumulation of stress that would lead to cracks and maintain structural integrity while preserving multi-layer connectivity.
Solution Approach 2:
The via structure employs a composite material architecture combining multiple metal layers with an intermediate buffer layer. This composite structure leverages the complementary properties of each material - the conductivity of metal layers and the stress-buffering capability of the intermediate layer - achieving both high connectivity and structural integrity simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes crack formation and leakage currents, enhancing the operational efficiency and reliability of semiconductor devices by managing thermal expansion disparities.
Implementation Method 1
Because of this difference in the coefficients of thermal expansion, it is possible that during processing of the semiconductor device cracks occur in or around the contact material of the through silicon via or in one of the metal layers
Data Source
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AI summary
A semiconductor device (10) comprises a semiconductor body (11), an electrically conductive via (12) which extends through at least a part of the semiconductor body (11), and where the via (12) has a top side (13) and a bottom side (14) that faces away from the top side (13), an electrically conductive etch-stop layer (15) arranged at the bottom side (14) of the via (12) in a plane which is parallel to a lateral direction (x), where the lateral direction (x) is perpendicular to a vertical direction (z) given by the main axis of extension of the via (12), and at least one electrically conductive contact layer (16) at the bottom side (14) of the via (12) in a plane which is parallel to the lateral direction (x). The etch-stop layer (16) is arranged between the electrically conductive via (12) and the contact layer (16) in the vertical direction (z), the lateral extent in the lateral direction (x) of the etch-stop layer (15) amounts to at least 2.5 times the lateral extent of the via (12) in the lateral direction (x), and the lateral extent of the contact layer (16) is smaller than the lateral extent of the via (12) or the lateral extent of the contact layer (16) amounts to at least 2.5 times the lateral extent of the via (12) .