Semiconductor Via Etching With Tungsten Hard Mask for Small CDs
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Solution Overview
Problem
During the back-end-of-line (BEOL) fabrication of semiconductor devices, the formation of via openings with small critical dimensions is challenging due to under etching issues caused by etching by-products, which can lead to poor electrical contact and increased complexity in the fabrication process.
Innovation Solution
The use of a hard mask comprising a tungsten-based material, such as tungsten carbide or tungsten nitride, reduces under etching by producing etching by-products with a lower boiling point that do not accumulate and block the via openings, allowing for more reliable formation of interconnect structures with smaller critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to form via openings with small critical dimensions, then the fabrication process becomes more complex with additional etching steps and etch stop layers, but under etching issues occur due to etching by-products accumulating and blocking the via openings
Solution Approach 1:
The patent changes the material parameter of the hard mask from conventional materials (such as silicon nitride or silicon oxide) to tungsten-based materials. This parameter change fundamentally alters the etching chemistry, producing by-products with lower boiling points that do not accumulate and block via openings, thereby enabling precise formation of small critical dimensions without requiring additional etching steps or etch stop layers
Solution Approach 2:
The patent exploits the phase transition properties of etching by-products. By selecting tungsten-based hard mask materials, the etching by-products are generated in a gaseous phase with low boiling point, allowing them to evaporate immediately rather than condensing and blocking the via openings. This phase behavior difference eliminates under etching issues and simplifies the fabrication process
2Device complexity
If the number of etching steps is reduced to simplify the fabrication sequence, then process complexity decreases, but achieving reliable electrical contact with small critical dimensions becomes more difficult
Solution Approach 1:
The patent changes the material composition parameter of the hard mask to tungsten-based materials, which fundamentally improves the etching process. This single parameter change enables the etching by-products to have favorable volatility characteristics, allowing complete via opening formation in fewer etching steps while maintaining or improving electrical contact reliability through better via opening quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication sequence by reducing the number of etching steps and etch stop layers needed, thereby improving the quality of via openings and ensuring better electrical contact with conductive features, while maintaining process complexity at manageable levels.
Implementation Method 1
etching by-products with a lower boiling point that do not accumulate and block the via openings
Data Source
AI summary
A method of forming a semiconductor device structure is disclosed. First and second etch stop layers are formed overlying a semiconductor structure having a conductive feature formed therein. A dielectric layer is formed overlying the second etch stop layer, and a hard mask, that comprises a tungsten-based material, is formed overlying the dielectric layer, and patterned. A resist layer is formed over the patterned hard mask. Using the patterned resist layer as a mask, a first etching process is performed to form a via opening that extends partially through the dielectric layer. Using the patterned hard mask as an etch mask, a second etching process (e.g., dry etching process) is performed to extend the via opening through the second etch stop layer, and a third etching process (e.g., wet etching process) is performed to extend the via opening through the first etch stop layer to reach the conductive feature.