Via-First Interconnection Process Using Conformal Dielectric Hard Mask
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Solution Overview
Problem
The current semiconductor manufacturing process using damascene techniques faces challenges with particle performance due to the generation of fluorinated and chlorinated polymers during etching, which impairs the etching process and affects subsequent manufacturing steps.
Innovation Solution
The process involves forming a substrate with a conductive region, a dielectric layer, and a patterned metal hard mask layer, followed by a conformally deposited dielectric hard mask layer. This setup allows for direct photolithography and etching without patterning the dielectric hard mask layer, preventing the reaction with fluoride-containing gases and reducing particle generation in the etching chamber.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If CF4-containing etching gas and Cl2-containing etching gas are used to etch SiON layer and metal hard mask layer respectively in one reaction chamber, then the etching process can be simplified, but fluorinated polymer and chlorinated polymer are simultaneously generated which impairs particle performance
Solution Approach 1:
The patent divides the etching process into two separate reaction chambers: the first chamber uses CF4-containing gas to etch the SiON layer, and the second chamber uses Cl2-containing gas to etch the metal hard mask layer. This segmentation prevents simultaneous generation of fluorinated and chlorinated polymers in the same chamber, thereby maintaining particle performance while still achieving process simplification through integrated chamber design.
Solution Approach 2:
The patent introduces an intermediary approach by using a specially designed reaction chamber that can handle multiple etching tasks sequentially. The chamber acts as an intermediary between the two different etching processes, allowing them to be performed in sequence rather than simultaneously, thus avoiding polymer contamination while maintaining manufacturing efficiency.
2Reliability
If multiple etching processes are performed in separate reaction chambers, then particle performance is maintained, but the manufacturing process becomes more complex
Solution Approach 1:
The patent merges multiple etching functions into a single reaction chamber that can perform sequential etching operations. The chamber is designed to handle both the SiON layer etching (using CF4-containing gas) and the metal hard mask layer etching (using Cl2-containing gas) in sequence, thereby maintaining particle performance while reducing the total number of reaction chambers needed and simplifying the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves particle performance during the etching process by eliminating the need for F-containing and Cl-containing gases, simplifying the manufacturing process, and enhancing the reliability of interconnect formation in semiconductor devices.
Implementation Method 1
a dielectric hard mask layer is formed conformally on the patterned metal hard mask layer
Implementation Method 2
a photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer in the trench opening
Implementation Method 3
a first etching process is performed with use of the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer
Data Source
AI summary
An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening.