Via-Free Interposer for Semiconductor Package Height Reduction
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Solution Overview
Problem
Current semiconductor packaging technologies rely on conductive through vias, which are costly and increase package size, limiting miniaturization and integration density.
Innovation Solution
An interposer design without conductive through vias, featuring a substrate portion with an electrical interconnect structure and a wall portion that exposes this interconnect structure, allowing semiconductor dies to be embedded within the interposer, reducing package height and fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive through vias are used to provide electrical connections for stacked semiconductor dies, then electrical performance and operation frequency are improved, but package size increases and fabrication cost increases
Solution Approach 1:
The patent extracts and eliminates the conductive through vias from the interposer structure, replacing them with a combination of exposed electrical interconnect structures on the substrate surface and conductive structures formed within recesses. This removal of unnecessary through-via components directly reduces package size while maintaining electrical connectivity functions through alternative pathways.
Solution Approach 2:
The patent implements nesting by placing semiconductor dies within recesses of the interposer structure, where the dies are embedded into cavities formed in the substrate. This nested arrangement allows the electrical interconnect structures to extend directly to the die bonding surfaces, eliminating the need for through-vias while achieving compact integration and reduced package volume.
2Reliability
If conductive through vias are used to provide electrical connections for stacked semiconductor dies, then electrical performance and operation frequency are improved, but fabrication cost increases
Solution Approach 1:
The patent removes the expensive through-silicon via fabrication process from the manufacturing workflow. Instead, electrical connections are achieved through surface-level electrical interconnect structures and conductive structures formed in recesses using standard semiconductor fabrication techniques, significantly reducing fabrication cost while preserving electrical performance.
Solution Approach 2:
The patent replaces expensive, complex through-via structures with simpler, cheaper alternative interconnection methods that use standard fabrication processes. The electrical interconnect structures on the substrate surface and conductive structures in recesses provide equivalent electrical functionality at lower manufacturing cost.
3Quantity of substance
If multiple semiconductor dies are stacked to achieve high integration density, then integration density is improved, but package height increases
Solution Approach 1:
The patent uses nesting by embedding semiconductor dies into recesses of the interposer, allowing multiple dies to be stacked in a compact vertical arrangement. The dies are positioned within cavities rather than on top of each other, which reduces the overall package height while maintaining high integration density through efficient vertical stacking.
Solution Approach 2:
The patent transitions from a traditional planar die arrangement to a three-dimensional stacked configuration where dies are embedded in vertical recesses. This dimensional change allows integration density to increase in the vertical direction without proportionally increasing package height, as the recesses utilize the substrate thickness dimension efficiently.
Data Source
AI summary
One aspect of the present disclosure provides an interposer for a semiconductor package. The interposer includes a substrate portion and a wall portion disposed on the substrate portion. The substrate portion has a first side, a second side, and an electrical interconnect structure between the first side and the second side. The substrate portion is substantially free from conductive through vias, and the cost for fabricating through silicon vias (TSV) is very expensive; therefore, the fabrication cost of the interposer can be dramatically reduced. In addition, the wall portion is disposed on the first side and defining an aperture exposing a portion of the electrical interconnect structure. At least one semiconductor die can be bonded to the interposer and inside the aperture. Consequently, the height of the semiconductor package is lower than the design of disposing the semiconductor die on top of the interposer.