Via Gouge Etch for Low Resistance Interconnects
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Solution Overview
Problem
Conventional semiconductor manufacturing technologies face challenges in creating interconnect structures with low resistance and mechanical strength, particularly at small geometries, where via to metal line interconnections exhibit high resistance and poor mechanical strength, leading to thermal cycling and stress migration failures.
Innovation Solution
The process involves etching a via gouge in the metal line before depositing dielectric and fabricating the overlying metal, allowing for improved control of via to metal line interconnects by making the via gouge before etching the via recess in the dielectric, which enhances mechanical strength and reduces resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If traditional via gouging process is used, then mechanical strength is improved, but manufacturing precision deteriorates due to mushroom-like shape formation
Solution Approach 1:
The patent applies preliminary action by performing the via gouge etch before depositing the capping layer and before etching the via recess. This sequence allows the via gouge to be formed with precise control of its depth and shape, preventing the mushroom-like profile that occurs when gouging is done after capping layer deposition. The preliminary formation of the via gouge ensures that subsequent processing steps can accurately define the via edges without encountering the undercut problems associated with traditional sequencing.
2Reliability
If via gouge is created to anchor vias, then reliability is improved, but device complexity increases due to additional process steps
Solution Approach 1:
The patent merges the via gouge formation step with the via recess etch step by using the same etch process to accomplish both functions. The via recess etch simultaneously defines the via opening through the capping layer and the via recess in the dielectric, while the previously formed via gouge provides the anchor. This consolidation reduces the number of separate process steps compared to traditional methods that require distinct gouging and recess formation steps, thereby reducing overall process complexity while maintaining reliability improvements.
3Productivity
If via dimensions are reduced for smaller geometries, then productivity is improved, but manufacturing precision deteriorates due to poor liner coverage
Solution Approach 1:
The patent applies preliminary action by forming the via gouge before depositing the capping layer and before etching the via recess. This sequence allows the via gouge to be formed with precise control of its depth and shape, preventing the mushroom-like profile that occurs when gouging is done after capping layer deposition. The preliminary formation of the via gouge ensures that subsequent processing steps can accurately define the via edges without encountering the undercut problems associated with traditional sequencing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more reliable interconnect structures with improved mechanical strength and reduced resistance, alleviating issues of mushroom-like via profiles and undercut problems, thereby enhancing the overall reliability and performance of integrated circuitry.
Implementation Method 1
A via gouge is etched in the first metal line. A first via recess is etch through the second dielectric layer where the first via recess aligned to the via gouge.
Implementation Method 2
A second dielectric layer is deposited over the first metal line and the first dielectric layer. A second metal layer is deposited in the first via recess and the via gouge, forming a first via.
Data Source
AI summary
An interconnection for a device in an integrated circuit includes a substrate on which a first metal line is embedded in a first dielectric layer. A via gouge is etched in the first metal line. A second dielectric layer is deposited over the first metal line and the first dielectric layer. A first via recess is etch through the second dielectric layer where the first via recess aligned to the via gouge. A second metal layer is deposited in the first via recess and the via gouge, forming a first via.