Via Hole Array Power Integrity in Semiconductor Packages
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Solution Overview
Problem
In the field of semiconductor packaging, there is a need for improved printed circuit boards and semiconductor package structures that maintain good power integrity (PI) due to increasing working frequencies and power consumption, particularly in high-speed and high-density applications.
Innovation Solution
A printed circuit board design featuring a via hole array with specifically arranged via holes to transmit power and ground signals, integrated with capacitors to reduce impedance and enhance power integrity, including a body with a first and second surface for bonding to a circuit substrate and capacitor, respectively, and a semiconductor package structure that includes these features to support high-density packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If working frequency and wiring density are increased to meet higher power consumption and multi-chip integration demands, then productivity and device capability are improved, but power integrity deteriorates due to increased impedance and signal interference
Solution Approach 1:
The via hole array is segmented into multiple via holes (first through sixth via holes) arranged in columns, where each via hole transmits either power signals or ground signals alternately. This segmentation allows for better control of impedance and power integrity by distributing the signal transmission across multiple controlled pathways rather than using single large vias or uncontrolled dense wiring.
Solution Approach 2:
Different regions of the printed circuit board are assigned different functions: the first surface bonds to the circuit substrate while the second surface bonds to capacitors. The via hole column units are periodically arranged to create local zones of optimized power and ground signal transmission. This local quality approach allows different parts of the board to be optimized for their specific functions while maintaining overall power integrity.
2Area of stationary object
If via holes are arranged in dense arrays to support high-density packaging, then area utilization is improved, but manufacturing precision requirements increase due to the need for precise alternating power and ground signal transmission
Solution Approach 1:
The via hole column units exhibit an asymmetric alternating pattern where power signal via holes and ground signal via holes are arranged in a specific non-uniform sequence (first, second, third, fourth, fifth, sixth via holes). This asymmetric arrangement is optimized to maintain proper impedance control and signal integrity while achieving high density, rather than using simple symmetric patterns.
Solution Approach 2:
The via holes are arranged in column units that extend in the vertical dimension through the board thickness, with multiple via holes stacked along the first direction. This dimensional approach allows high-density signal transmission by utilizing the Z-axis (board thickness) in addition to the X-Y plane, effectively increasing routing capacity without proportionally increasing lateral density requirements.
Data Source
AI summary
A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.