Via Hole Formation Using Patterned Blocking Layer Mask

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Solution Overview

Problem

Conventional lithography methods face challenges in creating via holes with pitches less than 90 nm and irregular arrangements, as they require multiple exposures and masks, limiting their applicability in integrated circuit manufacturing.

Innovation Solution

A method involving a substrate with defined regions, a dielectric layer, and a blocking layer, where the blocking layer is patterned and used as a mask to selectively etch via holes in desired areas, allowing for smaller pore sizes and irregular arrangements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional lithography with photo resist layer is used, then via holes can be formed with regular arrangement, but the pitch is limited to below 90 nm and irregular arrangements cannot be achieved

Engineering Contradiction:
Improvevia hole pitch and arrangement flexibilityVSAvoidlayout adaptability
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

A blocking layer is introduced as an intermediary between the substrate and the dielectric layer. This blocking layer serves as a sacrificial mask that enables precise via hole formation in irregular arrangements. The blocking layer is selectively removed in desired regions, allowing the etching process to create via holes only in specific locations with high precision, while maintaining flexibility for irregular layouts that conventional photo resist methods cannot achieve.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If dual exposing processes are used, then via holes with pitch below 90 nm can be formed, but the process complexity increases and irregular arrangements are not suitable

Engineering Contradiction:
Improvevia hole pitchVSAvoidexposure process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The blocking layer is patterned in advance to define the precise locations where via holes should be formed. This preliminary patterning step creates a mask structure that guides the subsequent etching process. By pre-defining the via hole positions in the blocking layer, the method achieves high precision for sub-90 nm pitches without requiring complex dual exposing processes, as the blocking layer pattern directly determines the via hole arrangement in a single etching step.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If photo resist layer serves as etching mask, then via holes can be formed, but the pore size is limited and cannot achieve smaller dimensions

Engineering Contradiction:
Improvevia hole pore sizeVSAvoidfeature size resolution
Core Design Contradiction:
Manufacturing precisionVSMeasurement precision

Solution Approach 1:

The invention changes the material parameter from conventional photo resist to a blocking layer with different properties. The blocking layer can be formed with thinner dimensions and higher precision, enabling via holes with smaller pore sizes. By altering the material parameters of the mask layer, the method overcomes the resolution limits of photo resist and achieves precise control over via hole dimensions at smaller scales.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9147601B2Method of forming via hole
Publication Date: 2015.09.29 UNITED MICROELECTRONICS CORP
  • US9147601B2 patent drawing
  • US9147601B2 patent drawing
  • US9147601B2 patent drawing

AI summary

The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned layer is formed on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer. The patterned layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.