Via Hole Constriction Etch Mask for Multilayer Substrates
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Solution Overview
Problem
The challenge in microelectronics and MEMS is forming high aspect ratio via holes with precise placement and controlled etching through substrates with multiple layers, as existing methods struggle with uncontrolled etching and limited precision due to differences in material etching rates and the need for conductive material deposition.
Innovation Solution
A method involving the formation of a via hole with a constriction that acts as an etch mask, using a combination of isotropic and anisotropic etching to create a narrowing aperture, allowing for precise and controlled opening of the via hole through substrates with multiple layers, and subsequent filling with conductive material for reliable interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a via hole is formed with high aspect ratio to improve precision in placement, then manufacturing precision is improved, but the ability to deposit conductive material on sidewalls deteriorates
Solution Approach 1:
The via hole formation process is segmented into multiple etching steps (first lengthwise portion and second lengthwise portion) with different etching directions. This segmentation allows creating a constriction that provides adequate sidewall exposure for conductive material deposition while maintaining high aspect ratio for precision placement.
Solution Approach 2:
The patent introduces a dimensional change in the via hole geometry by creating a constriction with a narrowing aperture. This dimensional feature (the constriction) provides additional surface area on sidewalls for conductive material deposition without increasing the overall via hole diameter, thus maintaining precision in placement.
2Ease of manufacture
If the via hole is widened to expose sidewalls for conductive material deposition, then ease of manufacture is improved, but precision in placement deteriorates
Solution Approach 1:
The via hole is designed with non-uniform geometry featuring a constriction that creates localized widening at specific regions. This local quality change provides adequate sidewall exposure for conductive material deposition only where needed, while maintaining narrow dimensions at other regions to preserve precision in placement.
3Device complexity
If conventional etching is used to form via holes through multilayer substrates, then device complexity is reduced, but manufacturing precision deteriorates due to uncontrolled etching
Solution Approach 1:
The etching process is segmented into multiple steps with different etching directions and conditions. This segmentation enables precise control over the via hole geometry, allowing the formation of a constriction with controlled aperture size and shape, thereby improving manufacturing precision while maintaining reasonable process complexity.
4Manufacturing precision
If the via hole aperture is controlled to maintain precision in placement, then manufacturing precision is improved, but the cross sectional area for electrical conduction deteriorates
Solution Approach 1:
The via hole geometry is designed with local quality variations, including a constriction that creates regions of different cross-sectional areas. The constriction provides adequate aperture for precision placement while the overall via hole structure maintains sufficient cross-sectional area for electrical conduction through the substrate.
Solution Approach 2:
The patent uses dimensional changes in the via hole geometry (creating a constriction with narrowing aperture) to decouple the relationship between aperture size and cross-sectional area. This allows optimizing precision in placement through controlled aperture while maintaining adequate cross-sectional area for electrical conduction through the via hole structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise and reliable formation of via holes that can extend through multilayer substrates, improving packaging efficiency and reducing electrical resistance, while maintaining high precision and reliability in component placement.
Implementation Method 1
etching a first and a second lengthwise portion of the via hole
Implementation Method 2
a conductive material is deposited, e.g. using a physical vapour deposition (PVD) process, on at least the sidewalls of the via hole
Data Source
Figure 1a~1e
Figure 2a~3d
Figure 4a~4c
AI summary
The present invention provides a method of forming a via hole (9), or a via (7), from a lower side (5) of a substrate (3) for electronic devices towards an upper side (4) of a substrate (3) at least partly through the substrate (3). The method comprises the steps of: etching a first lengthwise portion ( 1 1) of the via hole (9) and etching a second lengthwise portion ( 12) of the via hole (9); whereby the first lengthwise portion ( 1 1) and the second lengthwise portion (12) substantially form the via hole (9) and a constriction (23) is formed in the via hole (9). The constriction (23) defines an aperture (24) of the via hole (9) and the method further comprises the step of opening the via hole (9) by etching, with the constriction (23) functioning as an etch mask. A via is formed by at least partly filling the via hole with conductive material. A substrate for electronic devices comprising a via is also provided.