Via Hole Formation in Array Substrates Using Dual Patterning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of via holes in display panels is hindered by the risk of electro-static discharge (ESD) and surface damage due to uneven etching times and excessive exposure to etching gas, particularly when creating via holes of different depths in a single patterning process.
Innovation Solution
A method involving two patterning processes using separate masks to form a first via hole and an upper-part etched structure of a second via hole simultaneously, followed by a second process to complete the second via hole, reducing overall etching time and minimizing ESD risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single patterning process is used to form via holes of different depths, then the formation process is simplified, but some films are exposed to etching gas for excessive time causing surface damage and ESD
Solution Approach 1:
The patent divides the formation of via holes into two separate patterning processes: a first patterning process that forms via holes of a first depth, and a second patterning process that forms via holes of a second depth. This segmentation allows each process to be optimized independently, preventing excessive exposure of films to etching gas and reducing surface damage and ESD risks while maintaining manageable process complexity.
2Object-affected harmful factors
If two patterning processes are used to form via holes of different depths, then surface damage is reduced, but the actual etching time becomes excessively long and ESD probability increases
Solution Approach 1:
The patent performs the first patterning process to form via holes of a first depth before performing the second patterning process. This preliminary action allows the formation of shallower via holes to be completed first, reducing the cumulative etching time and minimizing the window for ESD events, while still achieving the benefit of reduced surface damage through the two-stage approach.
3Productivity
If a single patterning process is used, then production efficiency is maintained, but via hole formation time is excessive due to repeated etching
Solution Approach 1:
By segmenting the via hole formation into two targeted patterning processes rather than one repeated process, the patent reduces total formation time. Each process is optimized for specific depth requirements, eliminating redundant etching steps and improving overall production efficiency while maintaining high throughput.
4Length of stationary object
If excessive etching time is used to form deep via holes, then deep via holes are successfully formed, but films are exposed to etching gas for excessive time causing damage
Solution Approach 1:
The patent segments the via hole depth achievement into two stages: the first patterning process forms via holes to a first depth, and the second patterning process extends select via holes to a second depth. This segmentation allows deep via holes to be formed successfully while limiting the exposure time of films to etching gas in each individual process, preventing film damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the formation time of via holes, increases production efficiency, decreases the likelihood of ESD, and enhances product yield by allowing for precise control over the etching process and minimizing surface damage.
Implementation Method 1
forming a pattern of a first via hole and a pattern of an upper-part etched structure of a second via hole simultaneously on a base substrate through a first patterning process by using a first mask
Implementation Method 2
different etching time are actually required for forming the patterns of two via holes
Implementation Method 3
forming a pattern of the second hole in a region corresponding to the formed pattern of the upper-part etched structure of the second via hole through a second patterning process by using a second mask
Implementation Method 4
performing a dry etch process on a region corresponding to the formed pattern of the upper-part etched structure of the second via hole
Data Source
AI summary
The present disclosure provides a method of forming a via hole, an array substrate and a method of forming the same and a display device. The method of forming a via hole includes: forming a pattern of a first via hole and a pattern of an upper-part etched structure of a second via hole simultaneously on a base substrate through a first patterning process by using a first mask; forming a pattern of the second hole in a region corresponding to the formed pattern of the upper-part etched structure of the second via hole through a second patterning process by using a second mask.