TFT-LCD Array Substrate Via-Hole Etching Process
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Solution Overview
Problem
The existing via-hole formation process in TFT-LCD array substrates often results in over-etching and abnormal angles due to the use of a single etching process for both deep and shallow via-holes, leading to high connection resistance and defects like greenish and H-blocks.
Innovation Solution
A method that involves multiple etching processes to form via-holes in insulating layers, ensuring identical etching depth for both deep and shallow via-holes, preventing over-etching and abnormal angles, and reducing connection resistance by forming patterns simultaneously on insulating layers without additional patterning processes for conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single etching process is used to form both deep and shallow via-holes, then the manufacturing process is simple, but over-etching occurs and abnormal angles are formed
Solution Approach 1:
The patent divides the via-hole formation process into multiple etching steps: a first etching process to form shallow via-holes and a second etching process to form deep via-holes. This segmentation allows each etching process to be optimized independently, preventing over-etching and abnormal angles while maintaining manufacturing simplicity.
2Ease of manufacture
If transparent conductive metal wire is used to connect via-holes, then the connection is simple, but the connection resistance is too high
Solution Approach 1:
The patent changes the material parameter of the connection structure by using metal patterns instead of transparent conductive metal wires. This material substitution significantly reduces the connection resistance while maintaining the simplicity of the manufacturing process, as the metal patterns are formed simultaneously with the insulating layer patterns.
3Manufacturing precision
If additional patterning processes are performed on conductive layers, then the via-hole formation precision is improved, but the production cost increases
Solution Approach 1:
The patent merges the patterning of insulating layers and conductive layers into a single simultaneous patterning process. The metal patterns and insulating layer patterns are formed together in the same etching step, eliminating additional patterning processes and maintaining production cost efficiency while achieving precise via-hole formation.
Data Source
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AI summary
According to the method for manufacturing an array substrate of the present disclosure, when two non-adjacent conductive layers are electrically connected to each other through the via-holes, the insulating layers between the adjacent conductive layers may be etched by several etching processes so as to form the corresponding via-holes in the insulating layer, thereby to achieve the electrical connection between the non-adjacent conductive layers. Meanwhile, it is also able to achieve the electrical connection between the adjacent conductive layers through the via-holes in each etching process. In other words, when at least three conductive layers are electrically connected with each other through the via-holes, merely the insulating layer between the adjacent conductive layers is etched in each etching process, and there is no difference in terms of the deep via-hole and the shallow via-hole. As a result, it is able to prevent the occurrence of over-etching for the shallow via-hole as well as an abnormal angle of gradient, thereby to improve the yield and quality of the product.