Via Hole Formation with Partial Fill and CMP Planarization
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Solution Overview
Problem
Current methods for forming through-vias and redistribution layers in 3D chip assemblies face challenges such as incomplete filling of vias with conductive material, high material consumption, complex processes, and non-flat surface topologies, which hinder the denser interconnection and higher definition required for advanced 3D assemblies.
Innovation Solution
A method that simultaneously forms trenches in the insulation layer and fills both the via cavity and line patterns with conductive material, using chemical mechanical polishing to achieve a flat surface and better definition, allowing for partial filling of vias and separate control of via and line thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via cavities are completely filled with conductive material, then electrical connectivity is improved, but material consumption increases significantly
Solution Approach 1:
The patent applies partial filling of via cavities with conductive material. Instead of completely filling the via cavities, the method deposits conductive material to a controlled thickness that provides sufficient electrical connectivity while avoiding excessive material consumption. The via cavities are partially filled to establish electrical connection between redistribution layers without requiring complete filling, thus resolving the contradiction between connectivity reliability and material usage efficiency.
2Manufacturing precision
If multiple sequential steps are used to form via cavities and redistribution layers, then manufacturing precision can be controlled, but process complexity increases
Solution Approach 1:
The patent merges the formation of via cavities and redistribution layer patterns into a single simultaneous etching step. The method defines both the via cavity openings and the redistribution layer line patterns in one photolithography and etching sequence, rather than performing separate sequential operations. This consolidation maintains manufacturing precision for both structures while significantly reducing process complexity and the number of manufacturing steps required.
Solution Approach 2:
The patent performs preliminary definition of both via and line patterns simultaneously before conductive material deposition. By establishing the complete pattern geometry for both via cavities and redistribution lines in advance through a single masking and etching step, the method enables subsequent uniform filling operations while maintaining precise dimensional control, thereby reducing overall process complexity.
3Length of moving object
If high aspect ratio via cavities are formed, then vertical interconnection capability is improved, but filling difficulty and material consumption increase
Solution Approach 1:
The patent addresses high aspect ratio via filling by implementing partial filling to a controlled thickness rather than attempting complete filling. This approach maintains the deep via structure for effective vertical interconnection while avoiding the manufacturing difficulties and excessive material consumption associated with completely filling high aspect ratio cavities. The conductive material is deposited to a thickness sufficient for electrical connectivity without requiring complete via cavity occupation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces material consumption, simplifies the process, and achieves a flat, reliable surface for redistribution layers, enabling finer line widths and increased reliability of connections, suitable for multiple levels of interconnections and denser chip assemblies.
Implementation Method 1
a method that simultaneously forms trenches in the insulation layer and fills both the via cavity and line patterns with conductive material, using chemical mechanical polishing to achieve a flat surface
Data Source
Figure 1a~1b
Figure 2a~2b
Figure 2c~2d
AI summary
The method involves forming a cavity in a via on a face (220) of a substrate, and forming an insulating layer (240) on a lateral wall and a bottom part of the cavity and on the face of the substrate. A line pattern is formed on the face of the substrate, and a trench (244) is formed in a portion of the insulating layer located on the face of the substrate, where the trench opens into the cavity. The line pattern and the cavity are filled by electrically conducting material, where the cavity is not completely filled by the material.