Via Hole Electroplating Composition for Fast Void-Free PCB Filling
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Solution Overview
Problem
Conventional methods for filling via holes in printed circuit boards face issues such as prolonged processing times, excessive hydrogen gas generation, non-uniform plating, and reduced reliability due to voids and dimples, especially in narrow and deep skip vias, which conventional levelers cannot effectively address.
Innovation Solution
A leveler comprising specific structural units represented by Formulas 1 or 2, combined with a metal ion source, inhibitor, and brightener, is used in an electroplating composition, applying a pulse reverse current waveform to enhance filling efficiency and reduce voids and dimples.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high current is applied to reduce plating time and increase productivity, then productivity is improved, but excessive hydrogen gas is generated, additive decomposition is accelerated, plating becomes non-uniform, and reliability deteriorates
Solution Approach 1:
The patent employs pulse reverse current plating where the current direction periodically reverses. During the forward pulse, copper is deposited; during the reverse pulse, hydrogen gas is removed and additives are replenished. This periodic action allows high current density to be applied while maintaining plating uniformity and preventing excessive hydrogen accumulation, thus resolving the contradiction between productivity and reliability
Solution Approach 2:
The patent changes the electrical parameter from direct current to pulse reverse current, and optimizes parameters such as pulse width, duty cycle, and current density. By adjusting these parameters, the system achieves high deposition rates while controlling hydrogen evolution and additive consumption, thereby maintaining both high productivity and plating reliability
2Ease of manufacture
If conventional levelers are used for filling via holes, then the plating process can be performed, but voids and dimples occur in narrow and deep skip vias, reducing reliability
Solution Approach 1:
The patent introduces a novel leveler with specific molecular structure (containing imidazole or triazole rings with alkyl chains) that provides different functional properties at different locations. The leveler preferentially adsorbs on via hole walls and controls copper deposition locally within the via, ensuring uniform filling and preventing voids and dimples in narrow and deep skip vias, thus improving fill quality while maintaining manufacturability
3Reliability
If the plating process is extended to ensure complete via hole filling, then voids and dimples are reduced, but productivity decreases
Solution Approach 1:
The pulse reverse current plating enables complete via hole filling in shorter time by periodically removing hydrogen gas and replenishing additives during reverse pulses. This prevents plating defects that would otherwise require extended plating time to correct, thus achieving both complete filling and high productivity
Solution Approach 2:
The pulse reverse current system maintains continuous useful action by ensuring that during each forward pulse, copper deposition occurs efficiently, and during each reverse pulse, the plating environment is regenerated. This continuous cycle of deposition and regeneration ensures complete via filling without requiring extended total plating time, maintaining high productivity while ensuring reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves productivity and reliability by minimizing hydrogen gas generation and ensuring uniform plating, reducing production time while maintaining thin plating thickness and preventing voids and dimples in via holes.
Implementation Method 1
an electroplating composition comprising a metal ion source; the leveler; an inhibitor; and a brightener
Implementation Method 2
filling the via hole by performing electrolytic plating on the substrate on which the electroless plating layer is formed
Implementation Method 3
forming an electroless plating layer by performing electroless plating on the substrate on which the via hole is formed
Data Source
AI summary
The present invention relates to a leveler capable of efficiently filling the inside of via holes formed during the manufacturing process of a printed circuit board, and an electroplating composition comprising the same. When via holes on a substrate are filled with the electroplating composition according to the present invention, the via holes can be filled in a relatively short time while minimizing the formation of dimples or voids.


