Via Hole Routing Structure for Thin Substrates
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Solution Overview
Problem
In semiconductor and MEMS engineering, the close proximity of vias with different thermal expansion materials leads to cracking and reliability issues during manufacturing and use, and existing routing structures face challenges with thermal stress and topography, making it difficult to create cost-efficient vias and redistribution layers in thin substrates without compromising performance.
Innovation Solution
The method involves selective removal of insulating material from the bottom of blind holes without using lithographic steps, allowing for simultaneous creation of flush redistribution layers and vias, and using a seed layer technology that enables back-side plating without requiring complete coverage of vias, thus reducing thermal stress and topography issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vias are provided in very close proximity to each other, then routing density is improved, but thermal expansion effects cause substrate cracking and reliability issues
Solution Approach 1:
The patent changes the material parameter of the via filling from metal to dielectric material. This parameter change eliminates the thermal expansion coefficient mismatch between via material and substrate, preventing cracking while maintaining close via spacing for high routing density
Solution Approach 2:
The patent uses dielectric material for via filling that matches the substrate material properties, creating homogeneity in thermal expansion characteristics. This prevents stress concentration and cracking at via- substrate interfaces when vias are closely spaced
2Reliability
If conventional vias are completely filled with metal, then hermetic sealing is achieved, but thermal stress causes damage to thin chips
Solution Approach 1:
The patent changes the filling material parameter from metal to dielectric material. This eliminates thermal expansion mismatch while maintaining via fill integrity, preventing chip damage during temperature cycling without compromising hermetic sealing
Solution Approach 2:
The patent converts the previously harmful metal filling material into a beneficial dielectric material that provides both via fill integrity and thermal compatibility, turning a source of thermal stress into a solution that eliminates thermal stress
3Productivity
If substrate thickness is reduced to 100 μm for close via spacing, then via density is improved, but handling becomes impractical without carriers
Solution Approach 1:
The patent changes the via filling material to dielectric, which eliminates thermal expansion stress. This enables the use of thinner substrates (100 μm) without requiring carrier support, as the removed thermal stress prevents cracking during handling and processing
4Reliability
If thick Cu routing with reduced line width is used, then signal performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the via filling function with the routing insulation function by using dielectric material for via filling. This eliminates the need for separate thick Cu routing structures with reduced line widths, simplifying the overall routing structure while maintaining signal performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process of creating through-substrate vias and routing structures by eliminating the need for lithographic steps, reduces thermal stress, and allows for cost-effective production of thin substrates with efficient metal filling, enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
using a seed layer technology that enables back-side plating
Data Source
Figure 1a
Figure 1b
Figure 1c
AI summary
The invention relates to a method of providing a via hole and routing structure. A a substrate wafer having recesses and blind holes provided in the surface of the wafer is provided. An insulating layer is provided in the recesses and the holes, and the holes and recesses are metallized. The oxide layer in the bottom of the holes is removed to provide a contact between the back side and the front side of the wafer. The invention also provides a semiconductor device, comprising a substrate having at least one metallized via (V) extending through the substrate and at least one metallized recess forming a routing (RDL) together with the via (V). There is an oxide layer (ISO) on the front side field and on the back side field. The metal in the recess (RDL) and the via (V) is flush with the oxide (ISO) on the field on at least the front side, whereby a flat front side is provided. The thickness of the semiconductor device is < 300 µm.