Metal Via Structure With Conductive Hump for Current Crowding Relief

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Solution Overview

Problem

Existing FinFET manufacturing processes face challenges in forming reliable via structures at smaller sizes, leading to issues with electric current crowding and device performance.

Innovation Solution

The formation of a metal via with a selectively grown metal hump over the via structure, which increases the contact area and reduces interface resistance by using a conductive liner and fill metal material, mitigating electric current crowding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If via structures are formed at smaller sizes to support device scaling, then device density and integration are improved, but interface resistance increases and current crowding occurs

Engineering Contradiction:
Improvevia structure sizeVSAvoidinterface resistance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies local quality by creating a metal hump structure with varying cross-sectional area - wider at the base and narrower at the top. This non-uniform geometry concentrates conductive material where the interface contact area is smallest, locally enhancing electrical conductivity at the critical via-to-contact interface while maintaining overall via compactness for scaled devices.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs composite materials by combining multiple metal layers with different properties - a tungsten via structure complemented by a copper or aluminum metal hump. This composite approach leverages tungsten's mechanical strength and etch selectivity while utilizing copper's superior electrical conductivity to reduce interface resistance in the scaled via structure.

Inventive Principle:
Principle #40Composite materials

2Productivity

If via structure size is reduced for higher device density, then productivity is improved, but electric current crowding increases

Engineering Contradiction:
Improvedevice densityVSAvoidelectric current crowding
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent addresses current crowding in scaled vias by transitioning from a two-dimensional cross-sectional view to a three-dimensional structure with a metal hump. The hump adds vertical dimensionality with its tapered profile, creating expanded contact interfaces at multiple levels (via wall, via bottom, and top surface) that distribute current flow pathways and reduce crowding effects in miniaturized structures.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The metal hump structure introduces curved surfaces with varying radii - a rounded top surface and a tapered lateral profile - that naturally distribute current flow more evenly compared to sharp corners or flat surfaces. This curvature geometry reduces current concentration at specific points, mitigating current crowding in the scaled via structure.

Inventive Principle:
Principle #14Spheroidality (Curvature)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the performance of semiconductor devices by reducing interface resistance and preventing electric current crowding, enhancing the reliability of the device connections.

Implementation Method 1

A conductive liner is formed over the via structure. The conductive liner may include titanium nitride (TiN), tantalum nitride (TaN), or other suitable conductive materials

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

A metal hump is selectively grown over the via structure... The metal hump has a convex top surface and a plane bottom surface... to reduce interface resistance

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS11929321B2Method for forming via structure having low interface resistance
Publication Date: 2024.03.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11929321B2 patent drawing
  • US11929321B2 patent drawing
  • US11929321B2 patent drawing

AI summary

A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer over a substrate. A first metal feature is formed in the first insulating layer and a second insulating layer is formed over the first insulating layer. A first metal via is formed through the second insulating layer to connect the first metal feature. A second metal feature is formed over the second insulating layer. The second metal feature has a convex top surface and a plane bottom surface, and the plane bottom is electrically connected to the first metal feature through the first metal via.