Via-in-via Vertical Interconnect for High-Speed Signal Integrity

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Solution Overview

Problem

Current plated through hole vertical interconnect structures in printed circuit boards (PCBs) suffer from excessive impedance variation and cross-talk, limiting their ability to support high-speed signal transmission beyond 112 Gbps.

Innovation Solution

The implementation of a via-in-via vertical interconnect structure, which includes an inner plated cylinder inside an outer plated ground cylinder, providing continuous ground shielding and consistent impedance reference for high-speed signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional plated through hole structures are used, then manufacturing simplicity is maintained, but impedance variation and cross-talk increase

Engineering Contradiction:
Improvesignal transmission qualityVSAvoidinterconnect structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a via-in-via structure where an inner plated cylinder is nested inside an outer plated ground cylinder. This nested configuration provides continuous ground shielding around the signal path, maintaining consistent impedance reference and reducing cross-talk between adjacent vias, thereby improving signal transmission quality at high speeds.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Speed

If signal transmission speed is increased beyond 112 Gbps, then data transmission capability is improved, but impedance variation and cross-talk become excessive

Engineering Contradiction:
Improvesignal transmission speedVSAvoidsignal integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent ensures continuous ground shielding by maintaining the outer plated ground cylinder throughout the entire via structure. This continuous reference plane provides consistent impedance control along the signal path, enabling reliable high-speed transmission at 224 Gbps and beyond by preventing signal degradation from impedance discontinuities.

Inventive Principle:
Principle #20Continuity of useful action

3Object-affected harmful factors

If outer plating is removed between holes, then cross-talk is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvesignal cross-talkVSAvoidfabrication process simplicity
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The patent removes the outer plating material from the region between the first hole and the second hole. This extraction of conductive material eliminates the cross-talk path that would otherwise exist between adjacent vias, while the remaining plating on each individual via maintains its shielding function. The selective removal is achieved through targeted etching processes.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables reliable transmission of signals at speeds up to 224 Gbps by minimizing impedance discontinuities and reducing signal corruption due to cross-talk, while maintaining compatibility with traditional PCB fabrication processes.

Implementation Method 1

plating the inner cylinder and the outer cylinder with a conductive material to form an inner layer and an outer layer, respectively

Methodology Applied
Scientific EffectElectroplating: Electroplating

Implementation Method 2

filling the first, second, and third holes with a first non-conductive filler material; filling the fourth hole with a second non-conductive filler material

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS20250031318A1Plated via-in-via vertical connection
Publication Date: 2025.01.23 NOKIA SOLUTIONS & NETWORKS OY
  • US20250031318A1 patent drawing
  • US20250031318A1 patent drawing
  • US20250031318A1 patent drawing

AI summary

A method of manufacturing a via-in-via vertical interconnect in a printed circuit board (PCB), including: drilling a first hole through the PCB; drilling a second hole into a top side of the PCB; plating the first hole and the second hole with a conductive material to form an outer layer; drilling a third hole through the PCB wherein a portion of the plating is removed between the first hole and the second hole; filling the first, second, and third holes with an outer filler; drilling a fourth hole through the outer filler; plating the fourth hole with a conductive material to form an inner layer; filling the fourth hole with an inner filler; forming a via-in-via pad on top of the inner filler connected to the inner layer; and drilling a fifth hole through the bottom of the PCB along the fourth hole to remove a portion of the inner filler and inner layer wherein the top of the fifth hole is below the internal layer.