Via-Integrated Passive Devices in PoP Substrates

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Solution Overview

Problem

The challenge in the electronics industry is to reduce the size of integrated circuits, particularly in Package-on-Package (PoP) devices, where the available space between stacked packages is extremely limited, necessitating innovative packaging techniques to enhance electrical performance and operational frequency.

Innovation Solution

The Fan-in Package-on-Package (FiPoP) device integrates passive devices, such as capacitors and resistors, within vias of the substrate, using metal interconnections and dielectric or resistive materials to form high-capacity capacitors and resistors, respectively, which are electrically coupled to improve signal integrity and reduce size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If passive devices are integrated within vias of the substrate, then the size of the PoP device is reduced and electrical performance is enhanced, but the manufacturing complexity and precision requirements increase

Engineering Contradiction:
Improvesize of PoP deviceVSAvoidvia formation and filling precision
Core Design Contradiction:
Volume of moving objectVSManufacturing precision

Solution Approach 1:

The patent integrates passive devices (capacitors and resistors) within the vias of the substrate by nesting them inside the via structures. The via holes are filled with dielectric material and conductive materials to form capacitors, while resistive materials form resistors, effectively utilizing the via space for multiple functions including interconnection and passive device integration.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent combines multiple functions into the via structures: interconnection function (electrical connection between layers), capacitor function (by filling with dielectric and conductive materials), and resistor function (by filling with resistive materials). This merging of functions reduces the overall device size while integrating passive components directly into the substrate structure.

Inventive Principle:
Principle #5Merging (Combining)

2Length of stationary object

If the available space between top and bottom packages is reduced to minimize device height, then the overall device profile is smaller, but the electrical performance and signal integrity may deteriorate

Engineering Contradiction:
Improveheight of PoP deviceVSAvoidsignal integrity
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The patent transitions from planar integration to three-dimensional integration by stacking packages vertically and integrating passive devices within the substrate via structure. This dimensional change allows compact height while maintaining electrical performance through optimized via designs that provide adequate signal pathways and impedance control despite reduced spacing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent optimizes various parameters including via dimensions, material compositions, and filling ratios to maintain signal integrity despite reduced package spacing. By carefully controlling via diameter, wall thickness, and material properties, the design achieves reliable electrical connections and acceptable signal quality within the constrained vertical dimension.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances electrical performance, increases operational frequency, and reduces the resistive-capacitive (RC) delay and signal rising/falling time, making FiPoP devices more efficient than conventional PoP devices.

Implementation Method 1

a first via formed in the polymer layer and a material disposed in the first via to form a first passive device

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

using metal interconnections and dielectric or resistive materials to form high-capacity capacitors

Methodology Applied
Scientific EffectDielectric permittivity: Dielectric Permittivity

Implementation Method 3

using metal interconnections and dielectric or resistive materials to form high-capacity capacitors and resistors

Methodology Applied
Scientific EffectElectrical resistance: Electrical Resistance

Data Source

PatentUS10978433B2Package-on-package (PoP) device with integrated passive device in a via
Publication Date: 2021.04.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10978433B2 patent drawing
  • US10978433B2 patent drawing
  • US10978433B2 patent drawing

AI summary

A package for a use in a package-on-package (PoP) device and a method of forming is provided. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor.