Via-Integrated Resistor Structure for Simpler Semiconductor Fabrication

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Solution Overview

Problem

The manufacturing of semiconductor devices with both vias and resistors is complex and has a high error rate, requiring multiple masking and etching operations which decreases efficiency and increases cycle times.

Innovation Solution

The resistor is disposed within the via of the semiconductor device, with a metal plug and an oxide-based layer providing electrical insulation, and first and second landing pads with metal plugs for electrical connection, reducing the number of manufacturing operations and increasing tolerance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the resistor is placed outside the via, then the manufacturing process requires multiple masking and etching operations, but this increases complexity, error rates, and cycle times

Engineering Contradiction:
Improveerror rateVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the resistor formation process with the via formation process by placing the resistor within the via structure. This integration allows both features to be created simultaneously using the same masking and etching operations, eliminating the need for separate processing steps and reducing overall manufacturing complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The via structure serves multiple functions: it provides both the via connection and houses the resistor element. This multi-functionality reduces the total number of manufacturing operations required, as a single via formation process accomplishes what would traditionally require separate via and resistor formation steps

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If multiple masking and etching operations are used to manufacture vias and resistors separately, then manufacturing precision can be maintained, but productivity decreases and cycle times increase

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidcycle time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent combines the via and resistor formation into a single integrated process flow. By forming both structures simultaneously through coordinated masking and etching operations, the manufacturing cycle time is reduced and productivity is improved without sacrificing the required dimensional precision

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If the resistor is disposed within the via, then the number of manufacturing operations is reduced, but the structural complexity of the via increases

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidvia structure complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The resistor structure is nested within the via structure, with the resistor formed inside the via cavity. This nesting approach allows the resistor to be incorporated into the via without requiring additional external processing steps, simplifying the overall manufacturing process while the internal complexity is managed through precise deposition and etching control

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces the complexity and cost of the manufacturing process, decreases error rates, and shortens manufacturing time compared to placing the resistor outside the via.

Implementation Method 1

an oxide-based layer providing electrical insulation

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Data Source

PatentUS12347769B2Resistor within a via
Publication Date: 2025.07.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12347769B2 patent drawing
  • US12347769B2 patent drawing
  • US12347769B2 patent drawing

AI summary

In some implementations, one or more semiconductor processing tools may form a via for a semiconductor device. The one or more semiconductor processing tools may deposit a metal plug within the via. The one or more semiconductor processing tools may deposit an oxide-based layer on the metal plug within the via. The one or more semiconductor processing tools may deposit a resistor on the oxide-based layer within the via. The one or more semiconductor processing tools may deposit a first landing pad and a second landing pad on the resistor within the via. The one or more semiconductor processing tools may deposit a first metal plug on the first landing pad and a second metal plug on the second landing pad.