Via-First Interconnect Structure With Lower Via Contact Resistance
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Solution Overview
Problem
As semiconductor elements have been downscaled, the gap between circuit components like wirings has decreased, leading to an increase in resistance between the wiring and the via, which affects the reliability of semiconductor devices.
Innovation Solution
A semiconductor device and method where an upper wiring barrier layer is not formed on the upper surface of a via by forming a protective layer on the via during the process of forming the upper wiring pattern, thereby reducing contact resistance between the upper wiring pattern and the via.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an upper wiring barrier layer is formed on the upper surface of a via, then the wiring structure is protected and standardized, but contact resistance between the upper wiring pattern and the via increases
Solution Approach 1:
The patent extracts the barrier layer formation process from the via structure by using a protective layer that prevents the upper wiring barrier layer from being deposited on the via upper surface. This selective exclusion reduces contact resistance while maintaining the barrier layer's protective function elsewhere in the wiring structure.
Solution Approach 2:
The protective layer acts as an intermediary that temporarily covers the via upper surface during the barrier layer formation process. This intermediary layer prevents direct contact between the barrier layer and the via, thereby reducing contact resistance, and is subsequently removed to complete the structure.
2Productivity
If the gap between circuit components is decreased, then integration density increases, but resistance between wiring and via increases
Solution Approach 1:
The patent applies local quality by creating a specific condition at the via upper surface where the barrier layer is absent, while maintaining the barrier layer structure in other regions. This localized modification reduces contact resistance at the critical via-wiring interface without compromising the overall wiring structure's protective function.
Data Source
AI summary
A semiconductor device includes a substrate, a first interlayer insulating layer on the substrate, a lower wiring pattern inside the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer, a second interlayer insulating layer on the etch stop layer, a via trench inside the second interlayer insulating layer and the etch stop layer and that extends to the lower wiring pattern, a via inside the via trench and that is in contact with the second interlayer insulating layer and is formed of a single film, an upper wiring trench formed inside the second interlayer insulating layer on the via, and an upper wiring pattern inside the upper wiring trench and that includes an upper wiring barrier layer and an upper wiring filling layer on the upper wiring barrier layer An upper surface of the via is in contact with the upper wiring filling layer.