Via Interconnection Stress Relief for Semiconductor Electrode Terminals
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Solution Overview
Problem
The existing semiconductor devices face reliability issues due to stress concentration and cracking in the conductive layer of electrode terminals caused by the difference in coefficient of linear expansion between semiconductor chips and the mounting board, leading to potential interconnection breakdown and reduced mounting reliability.
Innovation Solution
Incorporating a via interconnection and a reinforcing member near the intersection of the semiconductor chip's outer edge line and the electrode terminal's circular arc part, which helps to alleviate stress and prevent cracks, thereby enhancing mounting reliability without increasing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrode terminals are mounted on the substrate, then electrical connection is achieved, but stress concentration and cracking occur in the conductive layer due to coefficient of linear expansion difference
Solution Approach 1:
The patent applies local quality by positioning via interconnections at specific locations where the outer edge line of the semiconductor chip intersects with electrode terminals. This localized reinforcement targets the exact areas experiencing maximum stress concentration, providing enhanced structural support precisely where needed without adding complexity to the entire device.
Solution Approach 2:
The via interconnections are formed in advance during substrate fabrication, creating preventive reinforcement structures before the semiconductor chip is mounted. This preliminary action ensures that the conductive layer is already strengthened at critical locations before stress from thermal expansion differences can cause cracking.
2Reliability
If via interconnection is added to reduce stress, then mounting reliability improves, but device complexity increases
Solution Approach 1:
Rather than adding via interconnections throughout the entire substrate, the patent applies them only at specific intersection points between the chip outer edge line and electrode terminals. This localized approach provides necessary stress relief while minimizing the overall increase in device complexity.
Solution Approach 2:
The patent implements a partial solution by adding via interconnections only at the most critical stress points rather than providing uniform reinforcement across the entire substrate. This partial action is sufficient to prevent cracking at the most vulnerable locations without the excessive complexity of comprehensive reinforcement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces stress on electrode terminals, improves mounting reliability, extends the range of heat-resistant temperatures, and prolongs the endurance time of semiconductor devices, particularly in environments with extreme temperature fluctuations.
Implementation Method 1
the via interconnection connecting a first interconnection layer on the first principal surface-side to a second interconnection layer on the second principal surface-side
Implementation Method 2
stress concentration and cracking in the conductive layer of electrode terminals caused by the difference in coefficient of linear expansion between semiconductor chips and the mounting board
Data Source
AI summary
A semiconductor device having a substrate, a semiconductor chip, and a plurality of electrode terminals is provided. The substrate has first and second principal surfaces. The semiconductor chip is disposed on the first principal surface. The electrode terminals are disposed on the second principal surface. The substrate has a via interconnection near a position at which an outer edge line of the semiconductor chip intersects an outer outline of the electrode terminal farthest from a center of the substrate, the electrode terminal farthest from the center of the substrate being among the plurality of electrode terminals overlapping the outer edge line in a predetermined condition as seen through the substrate of the semiconductor device from a direction perpendicular to the first principal surface, the via interconnection connecting a first interconnection layer on a first principal surface-side to a second interconnection layer on a second principal surface-side.