Via-Conductive Line Interface Without Barrier Layers

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Solution Overview

Problem

Conventional semiconductor fabrication processes face challenges in reducing contact resistance between vias and conductive lines, which is exacerbated by the presence of barrier layers that increase resistance.

Innovation Solution

The use of the same conductive material, such as ruthenium, for both the via and the conductive line eliminates the need for barrier layers, thereby reducing or eliminating contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If barrier layers are used between via and conductive line, then diffusion prevention is improved, but contact resistance increases

Engineering Contradiction:
Improvediffusion preventionVSAvoidcontact resistance
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The patent removes the barrier layer from the interface between the via and conductive line, extracting the harmful element that causes high contact resistance. The via is formed directly in contact with the conductive line without any intermediate barrier layer, thereby eliminating the resistance issue while maintaining diffusion prevention through alternative means.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses the same material for both the via and conductive line (e.g., both copper or both tungsten), creating a homogeneous interface. This material uniformity ensures low contact resistance and eliminates the need for barrier layers, as the identical materials are inherently compatible and do not require diffusion prevention interfaces.

Inventive Principle:
Principle #33Homogeneity

2Adaptability or versatility

If different materials are used for via and conductive line, then material optimization is improved, but contact resistance increases

Engineering Contradiction:
Improvematerial optimizationVSAvoidcontact resistance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies material homogeneity by using identical materials for both the via and conductive line. This eliminates material incompatibility issues and ensures low contact resistance, while still allowing overall material optimization by selecting the best single material (e.g., copper) for both components based on electrical performance requirements.

Inventive Principle:
Principle #33Homogeneity

3Ease of manufacture

If barrier layers are present at via-conductive line interface, then manufacturing process is improved, but circuit efficiency deteriorates

Engineering Contradiction:
Improvemanufacturing processVSAvoidcircuit efficiency
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The patent extracts and removes the barrier layer from the via-conductive line interface, eliminating the source of energy loss. By forming the via directly in contact with the conductive line without intermediate layers, the invention reduces contact resistance and improves circuit efficiency while maintaining manufacturability through simplified processes.

Inventive Principle:
Principle #2Taking out (Extraction)

4Stability of the object's composition

If multiple layers are used between via and conductive line, then structural stability is improved, but contact resistance increases

Engineering Contradiction:
Improvestructural stabilityVSAvoidcontact resistance
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The patent removes all intermediate layers between the via and conductive line, extracting the very structure that causes high contact resistance. The via is formed in direct contact with the conductive line, eliminating glue layers, barrier layers, and other intermediates that would increase resistance at the interface.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12266566B2Contact resistance between via and conductive line
Publication Date: 2025.04.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12266566B2 patent drawing
  • US12266566B2 patent drawing
  • US12266566B2 patent drawing

AI summary

A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.