Via Electrical Isolation in High-Density Integrated Circuits

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Self-aligned via structures in high-density integrated circuit devices fail to provide effective electrical isolation between vias and adjacent conductive layers.

Innovation Solution

A method involving the formation of recessed insulating and conductive layers, with selective deposition of additional insulating and conductive layers to enhance electrical isolation, including the use of blocking layers and etch stop layers to create openings and extend conductive layers through insulating layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a self-aligned via structure is used to enhance electrical isolation between via and adjacent conductive layer, then electrical isolation is improved, but the structure becomes ineffective in high density integrated circuit devices

Engineering Contradiction:
Improveelectrical isolationVSAvoideffectiveness in high density applications
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The insulating layer is segmented into multiple portions: a first insulating layer with a recess, a second insulating layer filling the recess, and a third insulating layer formed later. This segmentation creates a multi-level isolation structure that maintains electrical isolation effectiveness in high-density configurations where traditional single-layer self-aligned via structures fail.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from a planar self-aligned via approach to a three-dimensional recess structure. By creating a recess in the first insulating layer and filling it with a second insulating layer, the isolation structure gains vertical dimensionality, providing enhanced electrical isolation that remains effective even when horizontal spacing between vias is reduced in high-density applications.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If multiple insulating layers are formed to enhance electrical isolation, then electrical isolation is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical isolationVSAvoidnumber of insulating layers
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The recess is formed in the first insulating layer before subsequent processing steps. This preliminary action creates a pre-configured isolation structure that guides the formation of the second and third insulating layers, ensuring proper alignment and integration without requiring additional complex alignment steps or processes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The second insulating layer is formed to fill the recess and is self-aligned to the first insulating layer structure. The recess geometry itself defines the boundaries and positioning of the second insulating layer, eliminating the need for separate alignment procedures and reducing process complexity despite the additional layer.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively enhances electrical isolation between conductive layers in integrated circuit devices, improving performance in high-density applications.

Implementation Method 1

removing the blocking layer to form an opening in the second insulating layer

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

forming a second conductive layer extending through the third insulating layer. The second conductive layer may contact the first conductive layer

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS10957579B2Integrated circuit devices including a via and methods of forming the same
Publication Date: 2021.03.23 SAMSUNG ELECTRONICS CO LTD
  • US10957579B2 patent drawing
  • US10957579B2 patent drawing
  • US10957579B2 patent drawing

AI summary

Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a first conductive layer on a substrate and selectively forming a second insulating layer on the first insulating layer. The first insulating layer may include a recess, and the first conductive layer may be in the recess of the first insulating layer. The second insulating layer may include a first opening exposing a surface of the first conductive layer. The methods may also include forming a third insulating layer on the second insulating layer and the first conductive layer, forming a second opening extending through the third insulating layer and exposing the first conductive layer, and forming a second conductive layer in the second opening.