3D Chip-on-Wafer-on-Substrate Via Last Process
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Solution Overview
Problem
Current semiconductor packaging techniques face challenges in miniaturization, higher speed, and lower power consumption due to limitations in interconnections between stacked semiconductor wafers, particularly in achieving compact and efficient electrical connections.
Innovation Solution
The via last process is employed to form conductive vias through one or more dies after bonding, using self-aligning insulating spacers on the sidewalls of via openings to create narrower and taller vias, enhancing the aspect ratio and allowing for more compact via arrays and improved electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via formation processes are used before bonding, then the interconnection structure is established early, but the aspect ratio of vias is limited and warpage occurs during processing
Solution Approach 1:
The patent inverts the conventional sequence by forming vias after bonding rather than before. This reversal allows vias to be created through already-bonded substrates, enabling taller and narrower via structures with higher aspect ratios without the warpage issues that plague pre-bonding via formation processes.
Solution Approach 2:
The bonding process is performed as a preliminary action before via formation. By establishing the bonded substrate structure first, the patent creates a stable foundation that supports subsequent via formation with higher aspect ratios, eliminating the warpage problems that occur when vias are formed before bonding.
2Quantity of substance
If via openings are made narrower and taller to increase density, then inter-chip connection density improves, but manufacturing difficulty increases
Solution Approach 1:
By inverting the process sequence to form vias after bonding, the patent makes narrow and tall via openings manufacturable. The already-bonded substrate provides structural support that enables high-aspect-ratio via formation, achieving high inter-chip connection density without excessive manufacturing difficulty.
3Area of moving object
If stacked semiconductor devices are used to reduce form factor, then integration density increases, but interconnection complexity increases
Solution Approach 1:
The patent simplifies interconnection structures in stacked devices by inverting the via formation process. Forming vias after bonding enables more direct and simpler interconnection paths between stacked semiconductor devices, reducing overall device complexity while maintaining compact form factor.
Data Source
AI summary
Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.