3D Stacked-Chip Package Via Last Process
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller form factors and higher integration density while maintaining performance and reducing power consumption, as traditional packaging techniques are limited in miniaturization and interconnection efficiency.
Innovation Solution
The via last process is used to form self-aligning spacers within via openings, allowing for the creation of narrower and taller vias with improved aspect ratios, enabling more compact interconnections and facilitating the stacking of semiconductor dies without the need for discrete connectors like microbumps, thereby enhancing connectivity and reducing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional packaging techniques are used, then manufacturing process is simpler, but form factor cannot be sufficiently reduced and integration density is limited
Solution Approach 1:
The patent transitions from traditional 2D planar packaging to 3D vertical stacking architecture. Multiple semiconductor dies are stacked vertically with interconnect structures extending through mold compound, enabling three-dimensional interconnection topology. This dimensional change achieves superior integration density and miniaturization while maintaining electrical connectivity through the vertical stack configuration.
2Manufacturing precision
If wider vias are used, then manufacturing is easier, but interconnection density and compactness are reduced
Solution Approach 1:
The patent employs self-aligning spacers formed through conformal deposition processes that automatically define via dimensions. The spacer thickness, controlled by deposition parameters, precisely determines the via opening width. This parameter-controlled approach enables narrow via openings with high aspect ratios while maintaining manufacturing feasibility through the self-aligning mechanism that eliminates complex alignment steps.
3Reliability
If discrete connectors like microbumps are used, then electrical connection is established, but structure complexity and manufacturing steps increase
Solution Approach 1:
The patent merges the electrical interconnection function directly into the substrate and die structures through integrated via structures. Instead of separate discrete connectors, conductive vias are formed as integral parts of the interconnect system, extending through the mold compound to establish electrical pathways. This consolidation eliminates discrete connector components and simplifies the overall structure while maintaining reliable electrical connectivity.
Solution Approach 2:
The patent extracts and eliminates the discrete connector component from the interconnection system. By forming direct via structures that extend through the mold compound from substrate to die, the design removes the need for separate microbump or wire bond connectors. This extraction simplifies the structure, reduces manufacturing steps, and maintains electrical connection reliability.
4Quantity of substance
If more dies are stacked, then integration density increases, but warpage control becomes more difficult
Solution Approach 1:
The patent implements localized reinforcement structures including support posts and strengthened interconnect regions positioned at critical locations within the stack. These local quality enhancements provide mechanical support where needed most, controlling warpage in multi-die stacks without requiring uniform reinforcement throughout the entire structure. The selective placement of reinforcement elements addresses warpage control while maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher density inter-chip connections, improved warpage control, and a more heterogeneous chip stack, while simplifying the structure and reducing costs, allowing for more efficient packaging of semiconductor devices.
Implementation Method 1
forming self-aligning spacers within via openings
Implementation Method 2
forming self-aligning spacers within via openings
Implementation Method 3
forming conductive vias with the conductive vias extending through the second substrate
Implementation Method 4
forming conductive vias with the conductive vias extending through the second substrate
Implementation Method 5
bonding the first oxide layer of the first die to a second oxide layer of the second die with an oxide-to-oxide bond
Implementation Method 6
The commonly used bonding techniques include direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding
Implementation Method 7
thermo-compressive bonding
Implementation Method 8
thermo-compressive bonding
Data Source
AI summary
Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.