Via-Last TSV Stacking for Reliable Cross-Tier Wafer Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The design of complex system-on-chips (SoCs) is affected by through substrate via (TSV) volume deterioration in multi-stack wafers, leading to performance and complexity issues in cross-tier interconnect connections, particularly due to the increased number of interconnect levels in modern electronic devices.
Innovation Solution
A single-step via-last process for fabricating stacked integrated circuit (IC) dies using through substrate vias (TSVs) that extend through multiple semiconductor layers, allowing for cross-tier interconnect connections without volume loss, and enabling flexible wafer technology sourcing without the need for TSVs in the initial stacking process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through substrate vias (TSVs) are used for cross-tier interconnect connections in multi-stack wafers, then electrical connections between layers are established, but TSV volume deterioration occurs leading to performance degradation
Solution Approach 1:
The patent divides the TSV formation process into separate steps: first forming TSVs through the first substrate, then forming additional TSVs through the second substrate after stacking. This segmentation allows each TSV formation step to be optimized independently, preventing volume deterioration that would occur if all TSVs were formed in a single step through the entire multi-stack wafer.
Solution Approach 2:
The patent performs preliminary TSV formation in the first substrate before stacking with the second substrate. This preliminary action allows the first substrate's TSVs to be formed with optimal dimensions and properties, and subsequent TSVs in the second substrate can be formed after stacking to connect to the already-formed first substrate TSVs, maintaining consistent volume throughout the process.
2Adaptability or versatility
If multiple interconnect levels are added to support increased number of devices, then device interconnection capability is improved, but process complexity increases
Solution Approach 1:
The patent segments the interconnect formation process by creating TSVs in each substrate separately before stacking, rather than forming all interconnects in a single complex process. This allows each substrate to be prepared independently with its own optimized TSV structure, reducing overall process complexity while supporting multiple interconnect levels.
Solution Approach 2:
The patent transitions from planar interconnect expansion to three-dimensional stacking, adding the vertical dimension for interconnection. By forming TSVs in each substrate before stacking and then creating additional TSVs through the stacked structure, the patent enables multiple interconnect levels without proportionally increasing process complexity, as each layer can be processed independently.
3Adaptability or versatility
If TSV-based technology is used for multi-stack wafers, then cross-tier interconnect connections are enabled, but cost and complexity increase
Solution Approach 1:
The patent divides the manufacturing process into separate TSV formation steps for each substrate, allowing standard, well-established TSV formation techniques to be used for each individual substrate. This segmentation avoids the need for complex, expensive single-step TSV formation through entire multi-stack wafers, reducing manufacturing cost and complexity while maintaining cross-tier interconnect capability.
Solution Approach 2:
The patent performs preliminary substrate preparation and TSV formation before stacking, utilizing existing, cost-effective manufacturing processes. This preliminary action allows each substrate to be manufactured using standard processes, and the stacking step simply combines these pre-prepared substrates with additional TSV formation, significantly reducing overall manufacturing cost and complexity compared to forming all TSVs in a single complex process.
Data Source
AI summary
An integrated circuit (IC) is described. The IC includes a first die having a first semiconductor layer, a first active device layer and a first back-end-of-line (BEOL) layer. The IC also includes a second die having a second semiconductor layer, a second active device layer and a second back-end-of-line (BEOL) layer, and on the first die. The IC further includes a through substrate via (TSV) extending through the first die and the second die.


