Via Matrix Configuration for Electromigration Resistance
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Solution Overview
Problem
In semiconductor devices with multilayer wiring structures, electromigration (EM) causes voids and disconnection due to high current density, leading to increased via requirements, which in turn reduces margins between wires and increases the risk of insulating film peeling and reduced electron beam lithography throughput.
Innovation Solution
The method involves determining the life time change rates of via columns and rows, reducing the number of via columns based on these rates, and increasing the number of via rows to maintain or improve electromigration resistance while reducing the total number of vias, thereby preventing peeling and improving design margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of vias is increased to suppress electromigration, then electromigration resistance is improved, but the margin between adjacent wires is reduced and insulating film peeling risk increases
Solution Approach 1:
The patent transforms the via arrangement from a two-dimensional grid to a three-dimensional structure by introducing via stacks (multiple vias vertically aligned through different wiring layers). This vertical dimension allows current to be distributed across multiple layers, reducing the current density burden on any single via while maintaining overall electromigration resistance, thereby avoiding the need to increase lateral via density which would reduce wire margins and risk insulating film peeling.
Solution Approach 2:
The patent segments the current path by distributing it across multiple via stacks located at different positions within the via matrix. Instead of relying on a single dense via array, the current is divided and routed through multiple discrete via stacks, which reduces the current density per via and allows for greater spacing between vias, thus preserving wire margins and insulating film integrity.
2Reliability
If the number of vias is increased to handle higher current density, then electromigration resistance is improved, but the electron beam lithography throughput is reduced
Solution Approach 1:
By utilizing the vertical dimension with via stacks across multiple wiring layers, the patent reduces the number of lateral vias required in any single layer. This reduction in lateral via density decreases the lithography pattern complexity and exposure time, thereby improving electron beam lithography throughput while still providing sufficient current carrying capacity through the stacked via structure.
Solution Approach 2:
The via stacks serve multiple functions simultaneously: they provide electromigration resistance by distributing current, they reduce the lateral via count to improve lithography throughput, and they maintain electrical connectivity across multiple wiring layers. This multi-functionality allows a single structural element to address multiple competing requirements.
3Quantity of substance
If the via diameter is increased to reduce via count, then the number of vias is reduced, but the margin between adjacent wires is reduced
Solution Approach 1:
The patent compensates for reduced via count by exploiting the vertical dimension through via stacks. Multiple smaller vias are stacked vertically to create an equivalent or superior current carrying capacity compared to fewer larger vias. This approach maintains adequate wire margins while achieving the desired reduction in lateral via density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the number of vias while maintaining equivalent electromigration resistance, preventing peeling of insulating films, and enhancing electron beam lithography throughput by adjusting the via matrix configuration based on life time change rates.
Implementation Method 1
When high-density current flows through a fine wire included in a semiconductor device having a multilayer wiring structure, movement of electrons disturbs arrangement of atoms (such as cupper atoms or aluminum atoms) constituting the wire, which causes diffusion or migration of the metal atoms. This phenomenon is called electromigration (EM).
Data Source
AI summary
A designing method of a semiconductor device having a first wire and a second wire with a plurality of vias includes determining a first life time change rate of the semiconductor device in response to a change in a number of via column, a second life time change rate of the semiconductor device in response to a change in a number of via row, reducing the number of via column according to a ratio based on the first life time change and the second life time change; and increasing the number of via row at least one.