Via Structure for Hermetic MEMS Encapsulation
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Solution Overview
Problem
Current methods for producing semiconductor components with MEMS components in a hermetic cavity within a wafer stack are inefficient, unreliable, and economically costly, requiring complex process steps for movable MEMS structures and hermetic enclosure with simultaneous external electrical control.
Innovation Solution
A method involving an active wafer and a cover wafer, where MEMS structures are exposed by undercutting and a via area is formed through vertical trenches, allowing for hermetic enclosure and reliable electrical contacting within a wafer stack, using a single SOI wafer instead of two, reducing costs and process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex process steps are used to provide movable MEMS structures and hermetic enclosure with simultaneous external electrical control, then reliability and functionality are improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the hermetic enclosure formation and electrical contact establishment into a single integrated process. The via structure serves dual purposes: providing electrical connection through the wafer stack while simultaneously forming part of the hermetic enclosure when sealed with the cover wafer. This merging of functions reduces the number of separate process steps required.
Solution Approach 2:
The via structure performs multiple functions: it provides electrical connection between layers, serves as a pathway for vaporous reactant during undercutting, and becomes part of the hermetic seal when the cover wafer is bonded. This multi-functionality eliminates the need for separate dedicated structures for each purpose.
2Ease of manufacture
If traditional methods with two wafers are used for hermetic enclosure and electrical control, then functionality is achieved, but manufacturing cost and process steps increase
Solution Approach 1:
The patent merges the functions of two separate wafers into a single SOI wafer structure. The support layer, device layer, and insulating layer are integrated in one wafer, eliminating the need for a separate cover wafer while maintaining hermetic enclosure and electrical contact capabilities.
Solution Approach 2:
The single SOI wafer is segmented into functional layers (support layer, device layer, insulating layer) that perform different functions. This segmentation allows complex functionality to be achieved within a single wafer, reducing the need for multiple wafers while maintaining reliability.
3Reliability
If via structures are used for electrical connection, then electrical control is enabled, but parasitic capacitances and internal resistance increase
Solution Approach 1:
The via structure is optimized with specific geometric characteristics (narrow width, controlled depth) to minimize parasitic capacitance. The insulating layer surrounding the via further reduces parasitic effects by electrically isolating the via from adjacent conductive structures.
Solution Approach 2:
The insulating layer acts as an intermediary between the via and surrounding structures, reducing parasitic capacitance by providing electrical isolation. This intermediary layer allows the via to maintain its electrical connection function while minimizing harmful parasitic effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the production of robust, reliable, and cost-efficient semiconductor components with improved protection and functionality, allowing for compact and flexible integration of MEMS components with reduced parasitic capacitances and internal resistance.
Implementation Method 1
MEMS structures for the MEMS component are exposed by undercutting with a vaporous reactant, whereby a middle insulating layer of the active wafer is etched in the corresponding areas
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~1F
AI summary
The invention relates to a method for manufacturing a semiconductor device comprising a MEMS component in a hermetic cavity within a wafer stack formed by at least two wafers. For this purpose, an active wafer and a cover wafer are first provided. MEMS structures for the MEMS component are exposed by undercutting with a vaporous reactant, whereby a middle insulating layer of the active wafer is etched in the corresponding areas. In particular, a via is created on one of the wafers by forming vertical grooves, the via forming a vertical electrical connection. The via preferably has two terminals, an internal and an external one.The internal connection area of the via is contacted via a connection opening or a connection contact area, with both options having the contacts to the internal area located within the device layer of the active wafer. The external connection of the via is made via a connection pad. The method according to the invention is characterized in particular by the possibility of providing various MEMS components, especially gyroscopes, in a robust and cost-effective manner. In a further aspect, the invention relates to a semiconductor component that was manufactured according to the method according to the invention.