Via Mesh Layout Tuning for IC Timing and Electromigration
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Solution Overview
Problem
The optimization of via mesh specifications in integrated circuits is challenged by the need to balance timing improvement with increased density, which leads to interference and negatively affects chip performance, particularly due to varying cell pin layouts and power grid placement options.
Innovation Solution
A method involving a processor to optimize via mesh specifications by generating a new via mesh specification to address timing and electromigration issues, ensuring compliance with design rules and timing constraints, and replacing the existing mesh with the new one if the updated design passes checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If routing interconnections at higher metal layers with thicker metal wires, then timing is improved, but density increases leading to interference and negatively affecting chip performance
Solution Approach 1:
The patent applies local quality by creating different via mesh configurations tailored to specific cell types and their pin layouts. Instead of using a uniform via mesh design across the entire chip, the system generates customized via mesh specifications for different cells based on their individual placement options and power grid requirements. This localized approach allows optimization of timing for each cell while controlling interference in its specific vicinity.
Solution Approach 2:
The patent implements dynamics by making the via mesh configuration adaptable and variable rather than fixed. The system dynamically adjusts via mesh parameters such as via spacing, strap dimensions, and mesh density based on cell placement, power grid location, and timing requirements. This dynamic configuration enables the via mesh to optimize performance for different cells and placements while maintaining control over interference.
2Speed
If increasing via mesh density to improve timing, then timing is improved, but interference increases and negatively affects chip performance
Solution Approach 1:
The patent applies parameter changes by systematically varying via mesh parameters including via spacing, strap width, strap spacing, and mesh density to achieve optimal timing while controlling interference. The system adjusts these parameters based on cell type, placement location, and power grid configuration. By changing parameters locally rather than uniformly across the chip, the patent achieves timing improvement without proportionally increasing interference.
3Adaptability or versatility
If customizing via mesh for each cell's pin layout and placement, then routability is improved, but design complexity increases
Solution Approach 1:
The patent applies universality by creating a systematic framework that handles multiple cell types and configurations through a unified process. The via mesh generation system is designed to work with different cell types, pin layouts, and placement options using a consistent methodology. This universal approach improves routability for diverse cells while managing design complexity through automation and standardized procedures.
Solution Approach 2:
The patent implements self-service by enabling the via mesh design process to automatically adapt to different cell configurations without requiring manual intervention for each cell. The system self-adjusts via mesh parameters based on cell pin layouts, placement locations, and power grid positions, thereby improving routability while minimizing the complexity burden on designers.
Data Source
AI summary
Aspects of the invention include optimization of via mesh specifications in an integrated circuit. Aspects include obtaining a first mesh specification for a cell within an integrated circuit, identifying, based on a simulation of a first via mesh built based on the first via mesh specification, portions of the first mesh specification for enhancement, and generating a second mesh specification for the cell, wherein the second mesh specification is different from the first mesh specification. Aspects also include generating a second via mesh based on the second via mesh specification, updating a design of the integrated circuit by replacing the first via mesh with the second via mesh and connecting a top layer of the second via mesh to the net, and saving the updated design of the integrated circuit based on a determination that the updated design of the integrated circuit passes a timing and design rule check.