Semiconductor Via Mesh Layout for Higher Routing Freedom
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Solution Overview
Problem
Existing semiconductor fabrication methods face challenges in achieving high integration and routing freedom due to inefficient via structure design, leading to issues like insufficient routing tracks and adverse effects on device integration.
Innovation Solution
A method involving the generation and storage of X×Y via structures in a routing tool, where X and Y are integers between 1 and 20, allowing for the creation of a via structure with a mesh shape that maximizes the use of routing tracks and minimizes occupied area, thereby enhancing routing freedom and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional via structures are used in routing, then the routing process is simple, but the number of available routing tracks is insufficient and routing freedom is limited
Solution Approach 1:
The via structure is segmented into multiple individual vias arranged in a mesh pattern (e.g., 2x2, 3x3, or 4x4 arrays). Each via acts as an independent routing track, allowing multiple signal paths to coexist within a single via structure footprint. This segmentation transforms a single routing constraint into multiple routing opportunities, directly increasing routing freedom while maintaining manageable complexity through systematic arrangement.
Solution Approach 2:
The via structure transitions from a single-point connection to a two-dimensional mesh array. By distributing vias across a grid pattern rather than concentrating them at a single location, the invention adds spatial dimensionality to the routing capability. This dimensional expansion creates multiple lateral routing paths while the vertical via connections maintain electrical continuity, effectively increasing routing freedom without proportionally increasing overall footprint.
2Adaptability or versatility
If more routing tracks are provided to increase routing freedom, then the via structure occupies more area, but device integration is reduced
Solution Approach 1:
Multiple routing tracks are merged into a single via structure footprint by arranging multiple vias in a compact mesh pattern. Instead of providing separate via structures for each routing track, the invention combines multiple vias that share common upper and lower pad structures. This merging approach allows multiple routing paths to coexist within the area of a single conventional via structure, increasing routing freedom without proportionally increasing the occupied area.
Solution Approach 2:
The via structure is designed to serve multiple routing functions simultaneously. The mesh array of vias can accommodate different signal routes, power connections, and ground returns within the same structural footprint. The shared pad structures serve as universal connection points that can be accessed by multiple vias, allowing the same physical structure to fulfill multiple routing roles and reduce the total area required for diverse routing needs.
Data Source
AI summary
A method of fabricating a semiconductor device includes designing a layout of the semiconductor device, performing a routing step using a routing tool, performing an optical proximity correction (OPC) on the designed layout, and performing a photolithography process on a substrate using a photomask manufactured by the layout corrected by the OPC. Performing the routing step includes generating and storing an X×Y via structure in the routing tool, each of X and Y being an integer between 1 and 20, providing a low-level line and a high-level line, providing the X×Y via structure on a region where the low-level line and the high-level line overlap, and providing at least one routing line that passes through the X×Y via structure.