Universally Routable Via Mesh Specification Generation

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Solution Overview

Problem

Existing integrated circuit development methods fail to ensure universal routability of via mesh specifications, leading to routing issues due to varying cell placements and design rule violations.

Innovation Solution

Generating and selecting universally routable via mesh specifications that guarantee interconnectivity across all possible placements, using a computer-implemented method to define via mesh structures with specific strap and via configurations for each metal layer, ensuring compatibility with all design rules and timing requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If via mesh specifications are generated without verifying universal routability, then the design process is faster and less complex, but routing failures occur due to placement variations and design rule violations

Engineering Contradiction:

Improverouting success rateVSAvoidvia mesh specification verification complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by verifying universal routability of via mesh specifications before actual cell placement and routing. The system generates multiple test placements and attempts routing for each via mesh specification in advance, storing only those that succeed across all test placements. This preliminary verification ensures routing reliability is established before production use, preventing routing failures without adding complexity to the actual design flow.

Inventive Principle:

Principle #10Preliminary action

2Speed

If higher level metal layers are used for interconnections, then timing performance is improved, but density increases leading to increased interference and negatively affecting chip performance

Engineering Contradiction:

Improvesignal propagation speedVSAvoidinterference between interconnections

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by allowing different via mesh specifications (with different metal layer configurations) to be selected for different cells based on their specific placement and routing requirements. Rather than using a uniform via mesh specification across the entire chip, the system generates and stores multiple via mesh specifications with varying characteristics, enabling local optimization where high-speed routing is used where needed while maintaining lower density elsewhere, thus balancing timing performance with interference reduction.

Inventive Principle:

Principle #3Local quality

3Adaptability or versatility

If via mesh specifications are not verified for universal routability, then the library of via mesh specifications is smaller and easier to manage, but routing failures occur due to placement variations

Engineering Contradiction:

Improveplacement independence of via mesh specificationVSAvoidvia mesh specification generation efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by performing comprehensive routability verification across multiple test placements during the via mesh specification generation phase. The system generates candidate via mesh specifications, tests them against multiple placement scenarios, and retains only those that demonstrate universal routability. This upfront effort creates a library of highly adaptable specifications that work across diverse placements, eliminating the need for re-verification during actual design and improving overall productivity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent applies universality by designing via mesh specifications that function correctly across multiple placement scenarios. The verification process tests each via mesh specification against various cell placements and retains only those that succeed in all test cases. This creates a universal library where each via mesh specification can be applied regardless of the specific placement configuration, making the library highly versatile and placement-independent.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11341311B1Generation and selection of universally routable via mesh specifications in an integrated circuit

Publication Date: 2022.05.24 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Aspects of the invention include generating a set of via mesh specifications for a cell within an integrated circuit. Each via mesh specification defines one or more straps on each layer above a first layer, which includes one or more pins that form a pin terminal, to a top layer that connects the cell to a net for interconnection of the cell with one or more other cells, and also one or more vias that interconnect adjacent ones of the layers. Aspects also include verifying whether each via mesh specification is a universally routable via mesh specification guaranteeing that the cell interconnects with other cells through the net while meeting all design rules, and including only the via mesh specifications of the set of via mesh specifications that are universally routable in a library of via mesh specifications. The library is used to finalize and fabricate the integrated circuit.